Cyclical redundancy check method and apparatus

A cyclical redundancy check (CRC) generator which generates CRC information for error checking purposes, comprising:

• an interleaving circuit for dividing an input stream of data and producing a plurality of interleaves;
• a circuit which forms a linear combination of the plurality of interleaves and operates upon the linear combination in order to generate the CRC information;
• wherein the circuit which forms a linear combination of the plurality of interleaves and operates upon the linear combination in order to generate the CRC information comprises a plurality of sub-circuits, each sub-circuit comprising:
• an adder, the adder having a first input port, a second input port, and an output port, the first port of the adder having the plurality of interleaves multiplexed thereto;
• a multiplier, the multiplier having an output port thereof selectively connected to the second input port of the adder;
• a register for storing CRC information, the register having an input port connected to the output port of the adder and an output port selectively connected to the second input port of the adder.

A cyclical redundancy check (CRC) method which generates CRC information for error checking purposes, the method comprising:

• dividing an input stream of data and producing a plurality of interleaves;
• forming a linear combination of the plurality of interleaves and operating upon the linear combination in order to generate the CRC information by applying the plurality of interleaves to k number of sub-circuits for generating k bytes of CRC information with respect to the linear combination of interleaves, the sub-circuits being numbered from a first sub-circuit to a k.sup.th sub-circuit:
• and
• storing CRC information in a register of each sub-circuit and shifting CRC information stored in the register of the k.sup.th sub-circuit to the register of the first sub-circuit.

A cyclical redundancy check (CRC) method which generates CRC information for error checking purposes, the method comprising:

• dividing an input stream of data and producing a plurality of interleaves;
• forming a linear combination of the plurality of interleaves and operation upon the linear combination in order to generate the CRC information by applying the plurality of interleaves to k number of sub-circuits for generating k bytes of CRC information with respect to the linear combination of interleaves. the sub-circuits being numbered from a first sub-circuit to a k.sup.th sub-circuit;
• and
• comparing a CRC value inputted to a comparison one of the sub-circuits to CRC information stored in the register of the comparison sub-circuit.

A cyclical redundancy check (CRC) method which generates CRC information for error checking purposes, the method comprising:

• (a) dividing an input stream of data into a plurality of interleaves, the input stream being obtained from a communication channel;
• (b) forming a linear combination of the plurality of interleaves and operating upon the linear combination in order to generate the CRC information;
• (c) comparing the generated CRC information with decoded CRC information obtained from the communication channel;
• (d) producing an error signal when a discrepancy is detected between the generated CRC information and the decoded CRC information obtained from the communication channel;
• wherein the CRC information generated in step (b) constitutes K.sub.1 number of bytes stored in registers j=1, . . . k,
• wherein the decoded CRC information constitutes K.sub.1 number of decoded CRC bytes j=1, . . . k sequentially applied to a comparator, and
• wherein the comparison step comprises using the comparator to compare the contents of register j with decoded CRC byte j.

A cyclical redundancy check (CRC) method which generates CRC information for error checking purposes, the method comprising:

• (a) dividing an input stream of data into a plurality of interleaves, the input stream being obtained from a communication channel;
• (b) forming a linear combination of the plurality of interleaves and operating upon the linear combination in order to generate the CRC information;
• (c) comparing the generated CRC information with decoded CRC information obtained from the communication channel;
• (d) producing an error signal when a discrepancy is detected between the generated CRC information and the decoded CRC information obtained from the communication channel;
• wherein the CRC information generated in step (b) constitutes K.sub.1 number of bytes stored in registers j=1, . . . k;
• wherein the decoded CRC information constitutes K.sub.1 number of decoded CRC bytes j=1, . . . k sequentially applied to a comparator and wherein the comparison step comprises using the comparator to compare the contents of register j with decoded CRC byte j, and
• wherein K.sub.1 is a programmable integer.

A cyclical redundancy check (CRC) system comprising:

• a host port connected to a host device;
• a first CRC generator connected to the host port for generating primary CRC information based on input data received from the host device;
• a memory for storing therein input data received from the host device and the primary CRC information generated with respect thereto by the first CRC generator;
• a second CRC generator connected to the memory for generating verification CRC information for checking data retrieved from the memory;
• an encoder connected to form encoded information by utilizing the data retrieved from the memory including the primary CRC information;
• a utilization port connected to a utilization channel;
• a decoder connected to receive input data at the utilization port and to decode the input data into decoded input data including decoded CRC information, the decoder being connected to apply the decoded input data including the decoded CRC information to the second CRC generator and to the memory, the second CRC generator validating decoded CRC information included in the decoded input data, and
• wherein the first CRC generator is connected to receive decoded input data including the decoded CRC information stored in the memory for validating decoded CRC information received from the memory.

A cyclical redundancy check (CRC) method comprising:

• using a first CRC generator to generate primary CRC information based on input data received from a host device;
• storing in a memory the input data received from the host device and the primary CRC information generated with respect thereto by the first CRC generator;
• using a second CRC generator connected to the memory for generating verification CRC information with respect to data retrieved from the memory;
• forming encoded information by utilizing the data retrieved from the memory including the primary CRC information;
• decoding input data received from a utilization channel into decoded input data including decoded CRC information;
• applying the decoded input data including the decoded CRC information to the second CRC generator and to the memory;
• storing the decoded input data including the decoded CRC information in the memory;
• using the second CRC generator to validate the decoded CRC information included in the decoded input data;
• applying the decoded input data including the decoded CRC information from the memory to the first CRC generator;
• and
• using the first CRC generator to validate the decoded CRC information received from the memory.