US 5,671,234 AGranted

Programmable input/output buffer circuit with test capability

AssigneeCrosspoint Solutions, Inc.

InventorsChristopher E. Phillips, Michael G. Ahrens, Joseph G. Nolan, III, Laurence H. Cooke

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Abstract

An integrated circuit having system logic with programmable elements, decoding logic coupled to the programmable elements for addressing the programmable elements and a plurality of input/output buffer circuits for passing signals between the system logic and the exterior of the integrated circuit through input/output terminals is disclosed. Each input/output buffer circuit comprises an output driver stage having an output terminal connected to an input/output terminal; and a plurality of cells, each cell having a multiplexer, a flip-flop connected to an output terminal of the first multiplexer for storing a signal from the first multiplexer, a latch connected to an output terminal of the flip-flop for storing a signal from the flip-flop, and a second multiplexer connected to an output terminal of the latch. The cells connected to each other and cells of other input/output buffer circuits from an output terminal of the flip-flop of one cell to a first input terminal of a first multiplexer of another cell for serial scanning of signals through the cells to test the system logic. Control lines are connected to the output terminals of the latch of the cells and to the decoding logic coupled to the programmable elements so that the programmable elements can be addressed for programming by serially scanning control signals through the cells.

Claims12

Dependent claims

A CMOS circuit for driving a signal on an input terminal onto an output terminal, said circuit comprising:

a first pair of complementary transistors, a first transistor of said first pair having a gate electrode, a source electrode connected to a first voltage supply at a nominal first voltage, a drain electrode connected to said output terminal, a second transistor of said first pair having a gate electrode, a source electrode connected to a second voltage supply at a nominal second voltage, a drain electrode connected to said output terminal;
a second pair of complementary transistors for alternately turning one of said transistors of said first pair on at a time responsive to a signal on said input terminal, a first transistor of said second pair having a source electrode connected to a third voltage supply, a gate electrode to said input terminal and a drain electrode connected to said gate electrode of said first transistor of said first pair, a second transistor of said second pair having a source electrode connected to a fourth voltage supply, a gate electrode connected to said input terminal and a drain electrode connected to said gate electrode of said second transistor of said first pair, said third power supply at said nominal first voltage but not electrically connected to said first power supply, said fourth power supply at said nominal second voltage but not electrically connected to said second power supply;
and
a third transistor having a source electrode connected to said gate electrode of said second transistor of said first pair, a drain electrode connected to said fourth voltage supply and a gate electrode connected to said source electrode of said second transistor of said first pair;
whereby said output terminal is substantially immune from voltage spikes in said second voltage supply.

2 more elements

A CMOS circuit for driving a signal on an input terminal onto an output terminal, said circuit comprising:

a first pair of complementary transistors, a first transistor of said first pair having a gate electrode, a source electrode connected to a first voltage supply at a nominal first voltage, a drain electrode connected to said output terminal, a second transistor of said first pair having a gate electrode, a source electrode connected to a second voltage supply at a nominal second voltage, a drain electrode connected to said output terminal;
means connected to said input terminal and to said gate electrodes of said transistors of said first pair for alternately turning one of said transistors of said first pair on at a time responsive to a signal on said input terminal, said means coupled between a third and fourth power supply, said third power supply at said nominal first voltage but not electrically connected to said first power supply, said fourth power supply at said nominal second voltage but not electrically connected to said second power supply;
and
a third transistor having a source electrode connected to said gate electrode of said second transistor of said first pair, a drain electrode connected to said fourth voltage supply and a gate electrode connected to said source electrode of said second transistor of said first pair;
wherein said means comprises
a second pair of complementary transistors, a first transistor of said second pair having a source electrode connected to said third voltage supply, a gate electrode to said input terminal and a drain electrode connected to said gate electrode of said first transistor of said first pair, a second transistor of said second pair having a source electrode connected to said fourth voltage supply, a gate electrode connected to said input terminal and a drain electrode connected to said gate electrode of said second transistor of said first pair;
a third pair of complementary transistors, a first transistor of said third pair having a source electrode connected to said third voltage supply, a drain electrode connected to said gate electrode of said first transistor of said first pair and a gate electrode coupled to a first control terminal, a second transistor of said third pair having a source electrode connected to said fourth voltage supply, a drain electrode connected to said gate electrode of said second transistor of said first pair and a gate electrode coupled to said first control terminal;
and
at least one transistor having source and drain electrodes connected between said gate electrode of said first transistor of said first pair and said gate electrode of said second transistor of said first pair, and a gate electrode coupled to said first control terminal, said gate electrodes of said transistors of said third pair and said gate electrode of said at least one transistor coupled to said first control terminal so that said transistors of said third pair are on when said at least one transistor is off to disable said CMOS circuit, and off when said at least one transistor is on to enable said CMOS circuit;
whereby said output terminal is substantially immune from voltage spikes in said second voltage supply.

7 more elements

A CMOS circuit for driving a signal on an input terminal onto an output terminal, said circuit comprising:

a plurality of units, each unit connected in parallel to said input terminal and to said output terminal, each unit having
a control terminal;
means connected to said control terminal for enabling said each unit responsive to a signal on said control terminal;
and
means for driving a signal on said input terminal onto said output terminal with a predetermined drive current, said predetermined drive current being determined by each unit;
wherein said driving means of each unit comprises a first pair of complementary transistors, said transistors of said first pair connected in series between first and second nominal supply voltages, said transistors having gate electrodes of said transistors coupled to said input terminal and a commonly connected drain electrode connected to said output terminal, each transistor sized to provide said predetermined drive current through said output terminal when said transistor is conducting;
wherein said enabling means comprises
a second pair of complementary transistors, a first transistor of said second pair having a source electrode connected to a voltage supply at said first nominal voltage, a drain electrode connected to said gate electrode of said first transistor of said first pair and a gate electrode coupled to said control terminal, a second transistor of said second pair having a source electrode connected to a voltage supply at said second nominal voltage, a drain electrode connected to said gate electrode of said second transistor of said first pair and a gate electrode coupled to said control terminal;
and
a third transistor having source and drain electrodes coupled between said gate electrode of said first transistor of said first pair and said gate electrode of said second transistor of said first pair, and a gate electrode coupled to said control terminal, said gate electrodes of said transistors of said second pair and said gate electrode of said third transistor coupled to said control terminal so that said transistors of said second pair are on when said third transistor is off to disable said CMOS circuit, and off when said third transistor is on to enable said CMOS circuit;
whereby said circuit drives signals onto said output terminal with selective drive currents responsive to signals on said unit control terminals.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 08/078,692Filed 17 Jun 1993 · division
Priority: 21 Jun 1991
Granted: 23 Sep 1997
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

H03K 17/693
The devices being field-effect transistors: switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors
H03K 19/00361
Modifications for eliminating interference or parasitic voltages or currents: in field effect transistor circuits
H03K 19/018585
Using field effect transistors only: programmable
H03K
Pulse technique