Integrated circuit incorporating a test circuit

An integrated circuit to be mounted on a printed circuit board comprising:

• a plurality of signal terminals to be electrically connected to wires on said printed circuit board;
• a plurality of tristate buffers each for supplying a charging current to a stray capacitance of a corresponding wire on said printed circuit board through a corresponding signal terminal out of said plurality of signal terminals when an externally supplied test control signal designates a test mode, and for maintaining a high-impedance output when said test control signal designates a non-test mode;
• an input flip-flop for latching a test data signal in synchronism with a first test clock signal, and for distributing the test data signal thus latched to each of said plurality of tristate buffers;
• a plurality of logical gates each for supplying a logical signal having a pulse width indicative of a time interval between an input transition time of a corresponding tristate buffer out of said plurality of tristate buffers, and an output transition time of said corresponding tristate buffer;
• an AND gate for supplying a logical multiplication signal of said logical signals supplied from said plurality of logical gates;
• and
• an output flip-flop for latching said logical multiplication signal supplied from said AND gate in synchronism with a second test clock signal, and for externally supplying the logical multiplication signal thus latched.

An integrated circuit to be mounted on a printed circuit board comprising:

• a plurality of signal terminals to be electrically connected to wires on said printed circuit board;
• a plurality of tristate buffers each for supplying a charging current to a stray capacitance of a corresponding wire on said printed circuit board through a corresponding signal terminal out of said plurality of signal terminals when an externally supplied test control signal designates a test mode, and for maintaining a high-impedance output when said test control signal designates a non-test mode;
• a plurality of logical gates each for supplying a logical signal having a pulse width indicative of a time interval between an input transition time of a corresponding tristate buffer out of said plurality of tristate buffers, and an output transition time of said corresponding tristate buffer;
• a delay circuit for delaying an externally supplied test clock signal;
• an exclusive-OR gate for supplying, as an internal clock signal, an exclusive logical sum signal of said test clock signal and an output signal of said delay circuit;
• a plurality of selectors each for selecting, according to a logical value of said test clock signal, either the logical signal supplied from a corresponding logical gate out of said plurality of logical gates or a self-generated test data signal;
• and
• a plurality of flip-flops each for latching, in synchronism with said internal clock signal supplied from said exclusive-OR gate, a signal selected by a corresponding selector out of said plurality of selectors, and for supplying said latched signal to a corresponding tristate buffer out of said plurality of tristate buffers.