Low standby power redundancy circuit

A select circuit having circuit means to provide low standby power and an output free of transient pulses and comprising:

• (a) an output transistor connected in series with a gating transistor,
• (b) said gating transistor connected to circuit ground and the output transistor connected to Vcc through one or more bias transistors,
• (c) the input to said output transistor being a section select signal,
• (d) the input to said gating transistor being connected to two clamping transistors through a fuse device and to Vcc through a bias transistor,
• (e) each of said two clamping transistors further connected to circuit ground and one being controlled on or off by said section select signal and the other by a memory RAS signal,
• (f) said RAS signal preceding the section select signal, clamping off said gating transistor and preventing an error signal in the form of a transient pulse at the output of the select circuitry when said fuse device is conductive maintaining the connection of the clamp on the output circuitry,
• (g) said section select signal maintaining the clamp signal on said gating transistor input until said section select signal is removed and output transistor is off,
• (h) said fuse device when rendered non-conductive disconnecting clamping transistors from the circuit, allowing said gating transistor to be on and in turn allowing said output transistor to respond to section select signal.

A low power redundancy circuit for memory purposes providing addressing information for replacement of failing memory location and comprising:

• (a) multiple select circuits each containing a first fuse device and each connected to different sections of addressing circuitry,
• (b) said first fuse when rendered non-conductive activating the select circuit and allowing selection of said addressing circuitry,
• (c) said addressing circuitry consisting of multiple paths and each path of the addressing circuitry connected to an output of a select circuit,
• (d) a second fuse device in each address path connected in series between the output of the select circuit and the input to the addressing circuitry,
• (e) the connection between second fuse device and input to the addressing circuitry connected to Vcc through a bias transistor,
• (f) said bias transistor providing bias to output of select circuit through said second fuse device,
• (g) each said second fuse device when rendered conductive or non-conductive producing at the output of the paths of the addressing circuitry a signal with the value of a bit in the address of the failing memory location.

A clamp circuit controlling select circuit output off during and after a select signal transition comprising:

• (a) first and second clamp transistors connected in parallel between circuit ground and the input to a gating transistor through a fuse device,
• (b) said gating transistor connected in series with an output transistor which in turn is connected to Vcc through a bias transistor at its output,
• (c) signal input to said first clamp transistor being a memory RAS signal,
• (d) signal input to said second clamp transistor and the output transistor being a select signal,
• (e) the select and RAS signals being initially in a low voltage state controlling the clamp transistors off and the output transistor off and allowing the gating transistor to be biased on,
• (f) the output of the output transistor being in a high voltage state,
• (g) whereby when the RAS signal goes from a low voltage state to a high voltage state prior to the select signal going to a high voltage state controlling the gating transistor off,
• (h) the output transistor turning on when the select signal goes to a high voltage,
• (i) the output of the output transistor remaining high as a result of the gating transistor being held off by the RAS signal.

A select circuit comprising:

• (a) a transistor "nand" circuit with first input connected to the output of a transistor "nor" circuit and a bias transistor to Vcc,
• (b) the output of said "nand" circuit being the select circuit output,
• (c) said "nand" circuit and bias transistor separated from said "nor" circuit by a fuse device,
• (d) a select signal connected to the second input of said "nand" circuit and the first input of said "nor" circuit,
• (e) said "nor" circuit output controlling "nand" circuit off when select signal is present at the input of said "nor" circuit and fuse device in conductive,
• (f) a memory RAS signal applied to the second input of the "nor" circuit in advance of the select signal to prevent a transient pulse at the output of the select circuit,
• (g) the fuse device when rendered non-conductive disconnects the "nor" circuit output from the first input to the "nand" circuit and allowing said first input to the "nand" circuit to be biased on by the bias transistor,
• (h) a select signal applied to the second input of the said "nand" circuit when the fuse device is rendered non-conductive produces a signal at the output of said "nand" circuit.

A low standby power memory circuit for selecting addressing information to replace failing memory locations, and comprising:

• (a) a low standby power select circuitry activated by rendering a first fuse device non-conductive,
• (b) said select circuit, when activated, selecting a section of addressing paths through signal means,
• (c) each addressing path having a second fuse device when conductive or non-conductive providing addressing information to replace failing memory locations,
• (d) each address path grouped with other address paths into sections and each section providing the address of a different failing memory location,
• (e) multiple sections of addressing paths, each activated and selected by a separate select circuit and sharing address path output circuitry with other sections,
• (f) each section of address paths mutually exclusive of other sections of address paths with only one section being selected at a time,
• (g) each section of addressing paths providing a different address for a different failing memory location.