Random access memory having selective intra-bank fast activation of sense amplifiers
AssigneeAlliance Semiconductor Corporation
InventorsVipul C. Patel, Chitranjan N. Reddy
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Abstract
A dynamic random access memory (DRAM) (10) is disclosed. Memory cell arrays (12) within the DRAM have word lines and bit lines, the bit lines being logically divided into bit line sections (26a-p). Corresponding to each bit line section (26a-p) is a sense/decode section (28a-p) having a fast and slow sense mode of operation. When data are read from a particular bit line section (26a-p) the corresponding sense decode section (28a-p) operates in the fast sense mode while the remaining sense/decode sections (28a-p) operate in the slow sense mode, providing for lower power consumption and/or faster access speeds.
Claims21
In a random access memory having at least one array of memory cells, wherein a particular row of memory cells is coupled to a plurality of bit lines by activating selected word lines, a data sensing circuit, comprising:
- an array of sense amplifiers coupled to the bit lines for receiving memory cell data from the particular row of memory cells;
- each sense amplifier of said array of sense amplifiers being operable in a first mode in response to a first mode signal and a second mode in response to a second mode signal;
- sense amplifier decoding means for generating a first mode signal for a portion of the sense amplifier array in response to a first timing signal and at least a first decoding signal;
- and
- the first decoding signal is generated in response to at least one memory address input signal.
A random access memory, comprising:
- an array of memory cells;
- means for coupling memory cell data from said array of memory cells to a plurality of bit line outputs;
- amplifying means for providing a first amplification of the cell data on the bit line outputs;
- first decoding means for coupling a decoded bit line output to a data output in response to a first part of an externally applied address signal;
- and
- boost means for providing a second amplification of selected bit line outputs in response to at least a portion of the first part of the externally applied address signal, the decoded bit line output being one of the selected bit line outputs.
A random access memory, comprising:
- at least one array including
- a plurality of memory cells disposed in rows and columns, each row of cells including a plurality of primary word line segments formed from a first conductive layer,
- a plurality of secondary word lines formed from a second conductive layer, each secondary word line being coupled to the word line segments of a memory cell row by vertical interconnects;
- a plurality of bit lines formed from a third conductive layer disposed generally perpendicular to the primary word line segments;
- a plurality of sense amplifiers coupled to said plurality of bit lines, each sense amplifier having at least one activation node;
- at least one array sense enable device coupled to the sense nodes of said plurality of sense amplifiers;
- an array sense circuit for enabling said plurality of sense enable devices in response to an array clock signal;
- a plurality of section sense enable devices coupled to the sense nodes of said plurality of sense amplifiers;
- and
- a section sense circuit for enabling selected section sense enable devices in response to a section clock signal and a plurality of decoding signals.
Dependencies are inferred from the claim text.