Storage circuit
AssigneeTexas Instruments Incorporated
InventorsJimmie Don Childers, Seiichi Yamamoto, Masanari Takeyasu
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Abstract
A processor (10) comprises a plurality of processing elements each having an input register (11), first memory bank (12), first sense amplifier (40), ALU (13), output register (16), second memory bank (15) and second sense amplifier (42). The first sense amplifier (40) is shared between the input register (11) and first memory bank (12). The second sense amplifier (42) is shared between the output register (16) and second memory bank (15). The sense amplifier (40,42) may be paused to prevent voltage spikes during a readrite operation, or to wait until a calculation is completed.
Claims20
An integrated circuit having a first sense amplifier, said first sense amplifier comprising:
- first and second sensing nodes;
- high sensing circuitry for coupling a first voltage node associated with a first voltage source to one of said first or second sensing node responsive to a voltage differential between said first and second sensing nodes during a read portion of a read-modify-write cycle;
- third and fourth sensing nodes;
- low sensing circuitry for coupling a second voltage node associated with a second voltage source to one of said third or fourth sensing nodes responsive to a voltage differential between said third or fourth sensing nodes during said read portion of said read-modify-write cycle;
- coupling circuitry connected to said third and fourth sensing nodes for coupling a source of write data to said sense amp during a write portion of said read-modify-write cycle;
- and
- pause circuitry for selectively decoupling at least one of said voltage nodes from its respective voltage source prior to coupling said write data in order to prevent a low impedance connection between the voltage sources when said write data is coupled to said sense amplifier during said write portion of said read-modify-write cycle.
The sense amplifier of claim 11 wherein said low sensing circuitry comprises first and second n-channel transistors, said first n-channel transistor having a gate coupled to said fourth sense node, a first source/drain coupled to said second voltage node and a second source/drain coupled to said third sense node and said second n-channel transistor having a gate coupled to said third sense node, a first source/drain coupled to said second voltage node and a second source/drain coupled to said fourth sense node.
A method of operating a sense amplifier during a read-modify-write cycle comprising the steps of:
- sensing high signals responsive to a voltage differential between first and second sense nodes during a read portion of said read-modify-write cycle;
- coupling one of said first or second sense nodes to a high logic node responsive to said voltage differential between said first and second nodes;
- sensing low signals responsive to a voltage differential between third and fourth sense nodes during said read portion of said read-modify-write cycle;
- coupling one of said third or fourth sense nodes to a low logic node responsive to said voltage differential between said third and fourth nodes;
- selectively decoupling at least one of said voltage nodes from its respective voltage source after said read portion of said read-modify-write cycle and prior to a write portion of said read-modify-write cycle in order to prevent a low impedance connection between the first and second voltage sources.
Dependencies are inferred from the claim text.