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US 5,671,186 AGranted
Semiconductor memory device having bit line precharger
AssigneeFujitsu Limited
InventorKoichi Igura
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device includes a bit line, a memory cell, and a precharge circuit responsive to a precharge signal for charging the bit line. The precharge circuit is enabled before cell data is read from the memory cell via the precharged bit line. The memory device further includes a potential controller responsive to the precharge signal for regulating the charge applied to the bit line by the precharge circuit. A charge supplying circuit is coupled to the bit line, and maintains the bit line potential at a predetermined voltage level by providing the bit line with charges during a period from when the precharge circuit completes its precharge operation to when the bit line potential changes in response to reading data from the memory cell.
Claims18
A semiconductor memory device comprising:
- a memory cell including a cell transistor having a control gate, for storing cell data based on charges accumulated in the control gate of said cell transistor;
- a bit line connected to said memory cell;
- a precharge circuit responsive to a precharge signal being set one of high and low, for charging said bit line before the cell data is read from said memory cell and maintaining charging of said bit line in response to said precharge signal being set as the other of said high and low;
- and
- a potential control circuit responsive to said precharge signal for restricting the supply of charges applied to said bit line by said precharge circuit, said potential control circuit operating synchronously with the charging of said bit line by said precharge circuit.
2 more elements
A semiconductor memory device comprising:
- a memory cell including a cell transistor having a control gate, for storing cell data based on charges accumulated in the control gate of said cell transistor;
- a bit line connected to said memory cell;
- a precharge circuit responsive to a precharge signal being set one of high and low, for charging said bit line before cell data is read from said memory cell and maintaining charging of said bit line in response to said precharge signal being set as the other of said high and low;
- and
- a charge supplying circuit coupled to said bit line for maintaining the potential of said bit line at a predetermined voltage level by providing said bit line with charges during a period from when said precharge circuit completes charging said bit line to when the potential of said bit line changes in response to reading data from said memory cell.
2 more elements
A semiconductor memory device comprising:
- a cell transistor;
- a bit line connected to said cell transistor;
- a precharge circuit for applying a predetermined precharge voltage to said bit line;
- and
- a data output controller for detecting changeable bit line potential corresponding to the potential of charges stored in said cell transistor and for producing an output in accordance with the detected potential during the time cell data is read from said cell transistor,
- wherein said precharge circuit includes:
- a switch circuit, connected between a first power supply of a predetermined supply voltage and said bit line, for selectively connecting said bit line to said power supply in response to a precharge signal;
- and
- a voltage control circuit connected to said bit line, wherein said voltage control circuit operates in response to said precharge signal to produce the predetermined precharge voltage that is lower than the supply voltage of said power supply.
6 more elements
A semiconductor memory device comprising:
- a memory cell for storing cell data;
- a bit line connected to said memory cell;
- a precharge circuit responsive to a precharge signal for charging said bit line before cell data is read from said memory cell;
- and
- a potential control circuit responsive to said precharge signal for restricting the supply of charges applied to said bit line by said precharge circuit, said potential control circuit operating synchronously with the charging of said bit line by said precharge circuit, wherein said potential control circuit comprises a plurality of series connected transistors including one transistor provided between a high-potential power supply and said bit line and another transistor provided between said bit line and a low-potential power supply.
2 more elements
A semiconductor memory device comprising:
- a memory cell for storing cell data;
- a bit line connected to said memory cell;
- a precharge circuit responsive to a precharge signal for charging said bit line before cell data is read from said memory cell;
- and
- a potential control circuit responsive to said precharge signal for restricting the supply of charges applied to said bit line by said precharge circuit, said potential control circuit operating synchronously with the charging of said bit line by said precharge circuit, wherein said potential control circuit includes a depletion type MOS transistor provided between said precharge circuit and said memory cell, said depletion type M0S transistor having a gate and a drain connected together.
2 more elements
A semiconductor memory device comprising:
- a memory cell for storing cell data;
- a bit line connected to said memory cell;
- a precharge circuit responsive to a precharge signal for charging said bit line before cell data is read from said memory cell;
- a charge supplying circuit coupled to said bit line for maintaining the potential of said bit line at a predetermined voltage level by providing said bit line with charges during a period from when said precharge circuit completes charging said bit line to when the potential of said bit line changes in response to reading data from memory cell;
- and
- a hysteresis inverter as an output control circuit for detecting changeable bit line potential corresponding to the potential of charges stored in said memory cell and for producing an output in accordance with the detected potential,
- wherein said charge supplying circuit is provided between a power supply and said bit line and in parallel to said hysteresis inverter, and operates in response to the output of said hysteresis inverter based on the bit line potential when said memory cell is charged in a mode in which cell data is read, the bit line potential being maintained at said predetermined voltage level with power from said power supply.
4 more elements
A semiconductor memory device comprising:
- a cell transistor;
- a bit line connected to said cell transistor;
- a precharge circuit for applying a predetermined precharge voltage to said bit line;
- a data output controller, including a hysteresis inverter, for detecting changeable bit line potential corresponding to the potential of charges stored in said cell transistor and for producing an output in accordance with the detected potential during the time cell data is read from said cell transistor;
- a switch circuit, connected between a first power supply of a predetermined supply voltage and said bit line, for selectively connecting said bit line to said power supply in response to a precharge signal;
- and
- a voltage control circuit connected to said bit line, wherein said voltage control circuit operated in response to said precharge signal to produce the predetermined precharge voltage that is lower than the supply voltage of said power supply.
4 more elements
A semiconductor memory device comprising:
- a cell transistor;
- a bit line connected to said cell transistor;
- a precharge circuit for applying a predetermined precharge voltage to said bit line;
- a data output controller for detecting changeable bit line potential corresponding to the potential of charges stored in said cell transistor and for producing an output in accordance with the detected potential during the time cell data is read from said cell transistor;
- a switch circuit, connected between a first power supply of a predetermined supply voltage and said bit line, for selectively connecting said bit line to said power supply in response to a precharge signal;
- and
- a voltage control circuit connected to said bit line, wherein said voltage control circuit operated in response to said precharge signal to produce the predetermined precharge voltage that is lower than the supply voltage of said power supply, wherein said voltage control circuit includes a depletion type MOS transistor provided between said switch circuit and said cell transistor, said depletion type MOS transistor having a gate and a drain connected together.
4 more elements
A semiconductor memory device comprising:
- a cell transistor;
- a bit line connected to said cell transistor;
- a precharge circuit for applying a predetermined precharge voltage to said bit line;
- a data output controller including a hysteresis inverter for detecting changeable bit line potential corresponding to the potential of charges stored in said cell transistor and for producing an output in accordance with the detected potential during the time cell data is read from said cell transistor;
- a switch circuit, connected between a first power supply of a predetermined supply voltage and said bit line, for selectively connecting said bit line to said power supply in response to a precharge signal;
- a voltage control circuit connected to said bit line, wherein said voltage control circuit operated in response to said precharge signal to produce the predetermined precharge voltage that is lower than the supply voltage of said power supply;
- hysteresis inverter;
- and
- a feedback circuit, connected in parallel to said hysteresis inverter, operating in response to the output of said hysteresis inverter based on the bit line potential when said cell transistor is charged in a mode in which cell data is read, whereby the potential of said bit line is maintained at a predetermined voltage level.
6 more elements
A semiconductor memory device comprising:
- a bit line to read out stored data from a memory cell;
- a precharge circuit responsive to a first precharge signal to charge said bit line before the data is read from said memory cell, and to maintain charge on said bit line when said first precharge signal changes to a second precharge signal;
- and
- a charge supply circuit to maintain a predetermined voltage level on said bit line by providing charge when said precharge circuit completes charge of said bit line and by not providing charge during change in bit line potential during read out of the stored data from said memory cell.
1 more element
Dependencies are inferred from the claim text.