Apparatus for replacing defective cells in a memory device

A system for effecting repair or replacement of defective circuits in a solid state memory chip comprising:

• a memory chip having a fist block with only a group of mainline words and a second block with a group of mainline words and spare memory cells;
• a circuit means for switching from mainline words to spare memory cells including a first logic means having a first input always receiving a high voltage signal and a second input receiving said high voltage signal whenever repair is not selected for providing a first output whenever both inputs receive said high voltage signal and a second output at all other times, a second logic means having a first input connected to said output of said first logic means and a second input receiving a low voltage signal when repair is indicated, said second logic means having a first output whenever one of the inputs receives said high voltage signal and a second output whenever neither input receives said high voltage signal, and a third logic means having a first input connected to said output of said first logic means through a circuit that inverts the value of said output from said first logic means and a second input receiving said high voltage signal when repair is indicated, said third logic means producing a first output whenever both inputs receive said high voltage signal and a second output at all other times.