SRAM memory circuit and method of operation therefor

A SRAM memory device comprising:

• two memory sections, each memory section comprising:
• a plurality of column lines;
• a plurality of row lines;
• said plurality of column lines and plurality of row lines defining a matrix;
• a plurality of latches arranged in a plurality of substantially parallel first lines and a plurality of substantially parallel second lines, with the plurality of first lines substantially perpendicular to the plurality of second lines, each of said plurality of latches having a data node, and a first voltage node;
• wherein each of the latches arranged in the same first line has the same associated column line, and wherein each of the latches arranged in the same second line, has the same associated row line, with the first voltage node of each of the latches connected thereto;
• a plurality of avalanche diodes, each avalanche diode connecting the data node of a latch to its associated column line;
• first address decoder for decoding a first address signal and for selecting one of said plurality of column lines, in response thereto;
• second address decoder for decoding a second address signal and for generating one of a plurality of output signals in response thereto, each of said plurality of output signals having a corresponding row line;
• wherein the selection of one of said column lines and one of said row lines defines a select latch;
• and
• a plurality of voltage control circuit, each for receiving one of said plurality of output signals, and for applying a control signal to said corresponding row line, in response to a data read signal, a data write to one state signal or a data write to another state signal;
• a plurality of sense amplifiers, each for differentially sensing a select column line of a first memory section from a corresponding select column line of a second memory section.

A method of writing a select latch of a SRAM memory device to a first state or to a second state, said SRAM memory device having a plurality of first lines, a plurality of second lines, a plurality of latches arranged in a plurality of rows and columns with each latch having a data node, a first voltage node, and a second voltage node;

• each of said plurality of latches having an associated first line, and an associated second line, with said first voltage node connected to a first voltage source, and said second voltage node of said latches arranged in the same row connected to the same associated second line, having a second voltage supplied thereto;
• each of said plurality of latches further having an associated avalanche diode, with each avalanche diode connecting the data node of a plurality of latches arranged in the same column to the same associated first line;
• a first decoder for decoding a first address signal and for selecting one of said plurality of first lines, in response thereto;
• a second decoder for decoding a second address signal and for generating one of a plurality of output signals in response thereto, each of said plurality of output signals having a corresponding second line;
• and a plurality of voltage control means each for receiving one of said plurality of output signals, and for applying a control signal to said corresponding second line, said select latch having an associated select first line and an associated select second line, said method comprising:
• writing said select latch to said first state by:
• applying a third voltage to said associated select first line;
• lowering said second voltage on said associated select second line to a fourth voltage;
• conducting said avalanche diode associated with said select latch to maintain said data node at a fifth voltage, wherein said fifth voltage is between said first voltage and said fourth voltage;
• removing said third voltage applied to said associated select first line;
• writing said select latch to said second state by:
• applying a sixth voltage to said select first line;
• conducting said avalanche diode associated with said select latch to maintain said data node at a seventh voltage, wherein said seventh voltage is between said first voltage and said second voltage;
• raising said second voltage on said associated select second line to substantially said seventh voltage;
• and
• removing said sixth voltage applied to said select first line.

A method of reading a select latch of a SRAM memory device, said SRAM memory device having two memory sections, with each memory section having a plurality of first lines and a plurality of second lines with said plurality of first lines and plurality of second lines defining a matrix;

• the SRAM memory device further having a plurality of latches arranged in said matrix in a plurality of rows and columns with a reference cell in each column;
• each latch having a data node, a first voltage node having a first voltage supplied thereto, and a second voltage node;
• each latch arranged in the same column having an associated first line;
• each of said plurality of latches arranged in the same row having the same associated second line, with the second voltage node all connected to said same associated second line and with a second voltage supplied to said associated second line;
• a plurality of avalanche diode means, each avalanche diode means connecting the data node of a latch and a reference cell to its associated first line;
• first decoder means for decoding a first address signal and for selecting one of said plurality of first lines, in response thereto;
• second decoder means for decoding a second address signal and for generating one of a plurality of output signals in response thereto;
• each of said plurality of output signals having a corresponding second line;
• each of a plurality of voltage control means receives one of said plurality of output signals, and for applying a control signal to said corresponding second line;
• a plurality of sense amplifier means, each for differentially sensing a first line of a first memory section from a corresponding first line of a second memory section, said method comprising:
• applying said second voltage to all of said plurality of second lines of a first memory section, and to at least one second line of a second memory section, wherein said one second line of said second memory section being supplied to the reference cells of said second memory section;
• precharging a select one of said plurality of first lines of said first memory section, and a corresponding one of said plurality of first lines of said second memory section to a third voltage;
• changing said second voltage to a fourth voltage of one of said plurality of second lines of said first memory section thereby selecting said select latch defined by said one second line and said one first line;
• simultaneously changing said second voltage to a fourth voltage of another of said plurality of second lines of said second memory section thereby selecting a select reference cell defined by said another second line and said corresponding one first line of said second memory section;
• and
• differentially sensing the charge on said one first line of said first memory section and said corresponding one first line of said second memory section to determine the state of said select latch.

A method of reading a select latch of a SRAM memory device, said SRAM memory device having two memory sections, with each memory section having a plurality of first lines, a plurality of second lines, and a plurality of third lines, with said plurality of first lines and plurality of second lines defining a matrix, and with each third line having an associated second line;

• the SRAM memory device further having a plurality of latches arranged in said matrix in a plurality of rows and columns;
• each latch having a data node, a first voltage node, and a second voltage node;
• each latch arranged in the same column having an associated first line;
• each of said plurality of latches arranged in the same row having the same associated second line and the same associated third line, with the first voltage node of said latches in the same row all connected to the same associated third line, and with the second voltage node of said latches in the same row all connected to the same associated second line;
• a plurality of avalanche diode means, each avalanche diode means connecting the data node of a latch to its associated first line;
• first decoder means for decoding a first address signal and for selecting one of said plurality of first lines, in response thereto;
• second decoder means for decoding a second address signal and for generating one of a plurality of output signals in response thereto;
• each of said plurality of output signals having a corresponding second line and third line;
• each of a plurality of voltage control means receives one of said plurality of output signals, and for applying a control signal to said corresponding second line and corresponding third line;
• a plurality of sense amplifier means, each for differentially sensing a first line of a first memory section from a corresponding first line of a second memory section, said method comprising:
• applying a first voltage to all of said plurality of third lines of said first memory section;
• applying a second voltage to all of said plurality of second lines of said first memory section;
• precharging a select one of said plurality of first lines of said first memory section, and a corresponding one of said plurality of first lines of said second memory section to a third voltage;
• changing said second voltage to a fourth voltage of one of said plurality of second lines of said first memory section thereby selecting said select latch defined by said one second line and said one first line;
• simultaneously changing said first voltage to a fifth voltage of a third line corresponding to said one second line;
• differentially sensing the charge on said one first line of said first memory section and said corresponding one first line of said second memory section to determine the state of said select latch.