Data read circuit used in semiconductor storage device

A data read circuit used in a semiconductor storage device,

• the semiconductor storage device being provided with a bit line pair including two bit lines to which a memory cell is connected;
• the data read circuit comprising:
• a data line pair including two data lines and connected to the bit line pair, so that a data is read from the memory cell via the bit line pair to the data line pair in a data read operation and a data is written in the memory cell from the data line pair via the bit line pair in a data write operation;
• the data read circuit comprising:
• a latch type sense circuit connected to the data line pair for reading a data stored in the memory cell from the bit line pair to the data line pair;
• control transistors interposed between the bit line pair and the data line pair;
• and
• potential control means connected to control electrodes of the respective control transistors for controlling potentials of the control electrodes,
• wherein, in a data read operation where the latch type sense circuit is operated, the potential control means sets the potentials of the control electrodes of the control transistors at an intermediate potential that is smaller than a supply voltage but exceeds a ground voltage so as to operate the control transistors in a saturation region;
• and in the data write operation, the potential control means sets the potentials of the control electrodes of the control transistors at potentials which allow the control transistors to be operated in a linear region.

A data read circuit used in a semiconductor storage device

• the semiconductor storage device being provided with plural bit line pairs to which memory cells are connected and each bit line pair including two bit lines;
• the data read circuit comprising;
• a selector circuit which selects one pair of the bit line pairs among the corresponding plural bit line pairs for data read and write operations and includes CMOS transfer gates in the same number of the bit lines included in the plural bit line pairs, each of the CMOS transfer gates including a P-channel MOSFET and an N-channel MOSFET which are connected to each other at sources and drains thereof and the CMOS transfer gates being connected to the corresponding bit lines,
• a data line pair including two data lines which connected to each of the CMOS transfer gates, so that a data is read from the memory cell via the bit line pair to the data line in a data read operation and a data is written in the memory cell from the data line pair via the bit line pair in a data write operation;
• a latch type sense circuit connected to the data line pair for reading a data stored in the memory cell from the bit line pair to be selected by the selector circuit among the plural bit line pairs to the data line pair;
• and
• potential control means connected to respective gate electrodes of the MOSFETs of CMOS transfer gates for controlling potentials of the gate electrodes,
• wherein, in a data read operation where the latch type sense circuit is operated, the potential control means sets the potentials of the gate electrodes of two MOSFETs of CMOS transfer gates which are correspondingly connected to the bit line pair to be selected by the selector circuit at an intermediated potential that is smaller than a supply voltage but exceeds a ground voltage so as to operate the MOSFETs in a saturation region, and in the data write operation, the potential control means sets the potentials of the gate electrodes of two MOSFETs of CMOS transfer gates which are correspondingly connected to the bit line pair to be selected by the selector circuit at potentials which allow the MOSFETs to be operated in a linear region.