Non-volatile semiconductor storage apparatus
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorHiroshi Ueki
Life of this patent
Estimating the term…
Abstract
A non-volatile semiconductor storage apparatus which incorporates second bit lines connected to the sources of memory cell transistors arranged in a column direction, formed separately from the layer of first bit lines connected to the drains of the memory cell transistors arranged in a column direction. The apparatus is equipped with a system which can erase data byte by byte without enlarging the whole size irrespective of the provision of decoders in the first and second bit lines. A non-volatile semiconductor storage apparatus which erases data byte by byte by selecting a predetermined group of memory cell transistors by the source lines and the word lines connected to the diffusion area in the groups of memory cell transistors.
Claims7
A non-volatile semiconductor memory device comprising:
- a number of memory cell transistors arranged in row and column directions;
- word lines connected to the control gates of a plurality of memory cell transistors arranged in the row direction;
- a word line decoder for selecting at least one of said word line;
- a word line potential supplying means for supplying a first potential for the word line selected by said word line decoder during a first operating mode of the memory device, a second potential different from said first potential for the same during a second operating mode of the memory device, and a third potential different from said first and second potentials for the same during a third operating mode of the memory device;
- source lines connected to diffusion areas of memory cell transistor groups in the column direction, each of said memory cell transistor groups arranged in the column direction, each of said memory cell transistor groups having a predetermined number of the memory cell transistors whose control gates are connected to one of said word lines;
- a source line decoder for selecting at least one of said source lines;
- and
- a source line potential supplying means for supplying a fourth potential for the source line selected by said source line decoder during said first operating mode of the memory device, and a fifth potential different from said fourth potential for the same during said second or third operating mode of the memory device.
Dependencies are inferred from the claim text.