Semiconductor memory device including program inhibition capacitors and method for controlling program-disturb of non-selected memory cells
AssigneeSamsung Electronics Co., Ltd.
InventorsDong-soo Jang, Jung-dal Choi
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Abstract
An integrated circuit memory device includes a plurality of wordlines, a plurality of program inhibition lines, a plurality of serially connected memory cell transistors, and a plurality of program inhibition capacitors. Each of the memory cell transistors includes a gate connected to a respective one of the wordlines. Each of the program inhibition capacitors has a first terminal connected to a source/drain of a respective one of the memory cell transistors, and a second terminal connected to a respective one of the program inhibition lines. Related methods are also disclosed.
Claims26
An integrated circuit memory device comprising:
- a plurality of wordlines;
- a plurality of program inhibition lines;
- a plurality of serially connected memory cell transistors wherein each of said memory cell transistors includes a control gate connected to a respective one of said wordlines;
- and
- a plurality of program inhibition capacitors wherein each of said program inhibition capacitors has a first terminal connected to a respective one of said memory cell transistors and a second terminal connected to a respective one of said program inhibition lines.
A method for operating an integrated circuit memory device including a plurality of wordlines, a plurality of program inhibition lines, a plurality of serially connected memory cell transistors wherein each of said memory cell transistors includes a control gate connected to a respective one of said wordlines, a plurality of program inhibition capacitors wherein each of said capacitors has a first terminal connected to a respective one of said memory cell transistors and a second terminal connected to a respective one of said program inhibition lines, said method comprising the steps of:
- programming a selected one of said memory cell transistors by providing a program inhibition voltage to said plurality of program inhibition lines, by providing a program voltage to a selected one of said wordlines connected to said selected memory cell transistor, and by providing a pass voltage to all of said wordlines other than said selected wordline wherein said pass voltage is higher than a threshold voltage of one of said memory cell transistors and lower than said program inhibition voltage.
A method for programming a selected memory cell transistor of an integrated circuit memory device including a plurality of wordlines, a first plurality of serially connected memory cell transistors wherein each of said memory cell transistors of said first plurality includes a control gate connected to a respective one of said wordlines, and a second plurality of serially connected memory cell transistors wherein each of said memory cell transistors of said second plurality includes a control gate connected to a respective one of said wordlines, said method comprising the steps of:
- providing a program voltage to a selected one of said wordlines connected to said selected memory cell transistor of said first plurality of memory cell transistors;
- providing a pass voltage to all of said wordlines other than said selected wordline wherein said pass voltage is higher than a threshold voltage of one of said memory cell transistors;
- and
- boosting a potential of a channel region of a memory cell transistor of said second plurality of memory cell transistors connected to said selected wordline to a boost voltage on the order of at least about 70% that of the program voltage.
Dependencies are inferred from the claim text.