Shared rounding hardware for multiplier and divider/square root unit using conditional sum adder

A mantissa final addition and rounding unit that has a mantissa carry input and a mantissa sum input and that produces a rounded mantissa output, the mantissa final addition and rounding unit comprising:

• a conditional sum adder that takes a first adder input which includes upper bits of the mantissa carry input and a second adder input which includes upper bits of the mantissa sum input and that produces a first adder output and a second adder output, such that the first adder output represents an arithmetic addition of the first and second adder inputs and the second adder output is equal to one plus the arithmetic addition of the first and second adder inputs;
• a rounding mantissa processing unit that takes a first rounding input which includes lower bits of the mantissa carry input and a second rounding input which includes lower bits of the mantissa sum input and that produces a carry select signal;
• and
• a multiplexor that takes the first and second adder outputs and the carry select signal as inputs and that produces the rounded mantissa output, such that the rounded mantissa output equals the first adder output if the carry select signal is deasserted, and such that the rounded mantissa output equals the second adder output if the carry select signal is asserted.

An apparatus that produces a rounded mantissa output, the apparatus comprising:

• a first mantissa processing unit capable of producing a first mantissa in carry-save form such that the first mantissa has a first carry portion and a first sum portion;
• a second mantissa processing unit capable of producing a second mantissa in carry-save form such that the second mantissa has a second carry portion and a second sum portion;
• a multiplexor that takes the first and second mantissas as inputs and that produces a selected mantissa as output, such that the selected mantissa has a selected carry portion and a selected sum portion and is equivalent either to the first mantissa or the second mantissa;
• and
• a final addition and rounding unit that takes the selected carry portion and the selected sum portion as inputs and produces the rounded mantissa output, the final addition and rounding unit having a conditional sum adder that takes a first adder input which includes upper bits of the mantissa carry input and a second adder input which includes upper bits of the mantissa sum input and that produces a first adder output and a second adder output such that the first adder output represents an arithmetic addition of the first and second adder inputs and the second adder output is equal to one plus the arithmetic addition of the first and second adder inputs;
• a rounding mantissa processing unit that takes a first rounding input which includes lower bits of the mantissa carry input and a second rounding input which includes lower bits of the mantissa sum input and that produces a carry select signal;
• and
• a multiplexor that takes the first and second adder outputs and the carry select signal as inputs and that produces the rounded mantissa output, such that the rounded mantissa output equals the first adder output if the carry select signal is deasserted, and such that the rounded mantissa output equals the second adder output if the carry select signal is asserted.

A mantissa final addition and rounding unit that takes a mantissa carry input and a mantissa sum input and that produces a rounded mantissa output, the mantissa final addition and rounding unit comprising:

• a conditional sum adder that takes a first adder input which includes upper bits of the mantissa carry input and a second adder input which includes upper bits the mantissa sum input and that produces a first adder output and a second adder output, such that the first adder output represents an arithmetic addition of the first and second adder inputs and the second adder output is equal to one plus the arithmetic addition of the first and second adder inputs;
• a rounding mantissa processing unit that takes a first rounding input which includes lower bits of the mantissa carry input and a second rounding input which includes lower bits of the mantissa sum input and that produces a non-overflow mantissa portion, an overflow mantissa portion, a non-overflow carry signal, and an overflow carry signal as outputs;
• and
• a multiplexor taking the first adder output, the second adder output, the non-overflow mantissa portion, the overflow mantissa portion, and first and second multiplexor control signals as inputs and producing the rounded mantissa output, such that the rounded mantissa output is either the non-overflow mantissa portion appended to the first adder output, the non-overflow mantissa portion appended to the second adder output, the overflow mantissa portion appended to the first adder output, or the overflow mantissa portion appended to the second adder output.

A method of providing a floating point unit that produces a rounded mantissa output, the method comprising steps of:

• providing a first mantissa processing unit capable of producing a first mantissa;
• providing a second mantissa processing unit capable of producing a second mantissa;
• providing a multiplexor that takes the first and second mantissas as inputs and that produces a selected mantissa as output, such that the selected mantissa is equivalent either to the first mantissa or to the second mantissa;
• and
• providing a rounding unit that takes the selected mantissa as input and produces the rounded mantissa output, wherein the first mantissa is in carry-save format such that the first mantissa includes a first carry portion and a first sum portion.