Back to results
US 5,671,151 AGranted
Self-timed logic circuit having zero-latency overhead and method for designing same
AssigneeHaL Computer Systems, Inc.
InventorTed E. Williams
Life of this patent
Estimating the term…
Loading patent…
Loading patent…
AssigneeHaL Computer Systems, Inc.
InventorTed E. Williams
Estimating the term…
Asynchronous combinatorial logic apparatus and method are provided that propagate data through a logic array at the speed of a raw combinational logic array and generate a functional output signal. The apparatus and method provide a minimum expected value of data propagation delay. In one embodiment, a particular data path is identified that has higher than average usage probability based on knowledge of the probabalistic distribution of data values, and the particular data path connecting devices located in the identified higher usage path are modified, such as by shortening the path, so that the path that is known to have a higher usage is made faster. In another embodiment of a device implementing a combinational logic array needing a theoretical plurality of stages for executing the function is implemented with an asynchronous ring including a plurality of connected circuit stages wherein the plurality of stages is a smaller number of stages than the number of the theoretical plurality of stages, control logic for controlling the execution timing of the plurality of stages so that at least one of the plurality of stages executes more than once during the execution of the function, the apparatus thereby implements the theoretical plurality of stages in a smaller number of physical stages. In this manner, the apparatus achieves the performance of the larger combinational array having the theoretical plurality of stages in the smaller physical device area needed to implement the smaller number of circuit stages.
A method for implementing an asynchronous combinatorial logic apparatus that propagates data forward at the speed of a raw combinational logic array for generating a final functional output signal and having a minimum expected value of data propagation delay, said apparatus includes a plurality of data paths, and each of said paths receives at least one functional input signal and generates an intermediate functional output signal in response to said at least one functional input signal, said method comprising the steps of:
A method for implementing an asynchronous combinatorial logic apparatus that propagates data forward at the speed of a raw combinational logic array for generating a functional output from a functional input and having a minimum expected value of data propagation delay, said functional output being different from said functional input, said apparatus including a plurality of data paths, each of said data paths receives at least one functional input and generates an intermediate functional output in response to said at least one functional input, said method comprising the steps of:
An apparatus for implementing the execution of a function of a combinational array needing a theoretical plurality of stages for executing said function, said device comprising:
An apparatus for generating an output signal, comprising:
An apparatus for generating an output signal, comprising:
A method for implementing an apparatus for generating an output signal, said apparatus includes a plurality of paths, each of said paths receives at least one input signal and generates an intermediate signal in response to said at least one input signal, said method comprising:
Dependencies are inferred from the claim text.