Apparatus and method for checking logic circuit
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsMaho Urano, Miho Yokota
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Abstract
An apparatus and method for checking logic circuit checks logic element influenced by hot carriers in the logic circuit. The present invention comprises means for measuring rising transition time t.sub.r (or falling transition time t.sub.f) of signal generated by logic element comprising one portion of the logic circuit; means for calculating a ratio (DUTY) of rising transition time t.sub.r (or falling transition time t.sub.f) and operation period T of the signal; and means for comparing said DUTY with maximum allowable duty (DUTYMAX), in order to detect the logic element having DUTY exceeding maximum allowable duty (DUTYMAX).
Claims16
An apparatus for checking logic circuit comprising:
- means for measuring rising transition time t.sub.r (or falling transition time t.sub.f) of signal generated by logic element comprising one portion of the logic circuit;
- means for calculating a ratio (DUTY) of rising transition time t.sub.r (or falling transition time t.sub.f) and operation period T of the signal;
- and
- means for comparing said DUTY with maximum allowable duty wherein, if the comparison result is DUTY<DUTYMAX, it is judged that hot carriers give a small effect on the logic element, and if the comparison result is DUTY>DUTYMAX, it is judged that hot carriers give a large effect on the logic element.
An apparatus for checking logic circuit comprising:
- means for measuring capacitance Ci and Cpi of each load driven by a logic element;
- means for calculating total capacitance Cout (.SIGMA.Ci+.SIGMA.Cpi) of these loads;
- means for comparing said calculated Cout with maximum allowable capacitance Cmax;
- means for measuring rising transition time t.sub.r (or falling transition time t.sub.f) of signal generated by logic element comprising one of the logic circuit;
- means for calculating a ratio (DUTY) of rising transition time t.sub.r (or falling transition time t.sub.f) and operation period T of the signal;
- and
- means for comparing said DUTY with maximum allowable duty (DUTYMAX) for logic elements where Cout exceeds the maximum allowable capacitance Cmax;
- wherein, if the comparison result is DUTY<DUTYMAX, it is judged that hot carriers give a small effect on the logic element and if the comparison result is DUTY>DUTYMAX, it is judged that hot carriers give a large effect on the logic element.
An apparatus for checking logic circuit comprising:
- means for measuring t.sub.ri and t.sub.fi of a signal applied to a signal line;
- means for calculating .SIGMA.t.sub.ri, defined as a first total transition time;
- means for calculating .SIGMA.t.sub.fi, defined as a second total transition time;
- means for measuring a period T of the signal directly or assigning a value of period T of a predetermined signal;
- means for calculating a DUTY by a following formula:
- DUTY=(.SIGMA.t.sub.ri !+.SIGMA.t.sub.fi !)/2T;
- and
- means for comparing the DUTY with a specific maximum duty DUTYMAX of a logic element;
- wherein, if the comparison result is DUTY<DUTYMAX, it is judged that hot have a small effect on the logic element and if the comparison result is DUTY>DUTYMAX, it is judged that hot give a large effect on the logic element.
An apparatus for checking a logic circuit, the logic circuit including a logic element coupled to the apparatus by a signal line, a plurality of loads comprising:
- means for measuring respective capacitances Ci and Cpi of the plurality of loads of the logic element;
- means for calculating total capacitance Cout (.SIGMA.Ci+.SIGMA.Cpi) of said loads;
- means for comparing said calculated Cout with maximum allowable capacitance Cmax;
- means for measuring t.sub.ri and t.sub.fi of a signal applied to the signal line;
- means for measuring a first total rising transition time .SIGMA.t.sub.ri ;
- means for measuring a second total falling transition time .SIGMA.t.sub.fi ;
- means for measuring a period T of the signal or assigning a value period T of a predetermined signal;
- means for calculating DUTY by a following formula;
- DUTY=(.SIGMA.t.sub.ri +.SIGMA.t.sub.fi)/2T
- means for comparing DUTY with a specific maximum duty DUTYMAX of the logic element;
- wherein, if a comparison result is DUTY<DUTYMAX, it is judged that hot carriers have a small effect on the logic element and if the comparison result is DUTY>DUTYMAX, it is judged that hot carriers give a large effect on the logic element.
A method for checking the effects of hot carriers on a logic circuit, the logic circuit including a logic element, said method comprising:
- measuring rising transition time t.sub.r or falling transition time t.sub.f of a signal generated by the logic element;
- calculating a ratio (DUTY) of rising transition time and an operation period T of the signal;
- and
- comparing said DUTY with a maximum allowable duty (DUTYMAX),
- wherein, if a comparison result is DUTY<DUTYMAX, it is judged that hot carriers have a small effect on the logic element, and if the comparison result is DUTY<DUTYMAX, it is judged that hot carriers have a large effect on the logic element.
A method for checking the effects of hot carriers on a logic circuit, the logic circuit including a plurality of signal lines and a capacitor and a load connected to each signal line, and a logic element coupled to the plurality of signal lines, said method comprising the steps of:
- measuring capacitances Ci and Cpi of each load driven by the logic element;
- calculating a total capacitance Cout (.SIGMA.Ci+.SIGMA.Cpi);
- comparing said calculated Cout with maximum allowable capacitance Cmax;
- measuring rising transition time t.sub.r or falling transition time t.sub.f of a signal generated by the logic element;
- calculating a ratio (DUTY) of rising transition time t.sub.r or falling transition time t.sub.f or falling transition time t.sub.f and an operation period T of the signal;
- and
- comparing said DUTY with maximum allowable duty (DUTYMAX) for logic elements where Cout exceeds the maximum allowable capacitance Cmax;
- wherein, if a comparison result is DUTY<DUTYMAX, it is judged that hot carriers have a small effect on the logic element and if the comparison result is DUTY>DUTYMAX, it is judged that hot carriers have a large effect on the logic element.
A method for checking the effects of hot carriers on a logic circuit, the logic circuit including a logic element coupled to a signal line, said method comprising the steps of:
- measuring a rising transition time t.sub.ri and a falling transition time tfi of a signal applied to the signal line;
- calculating the total rising transition time .SIGMA.t.sub.ri ;
- calculating the total falling transition time .SIGMA.t.sub.fi ;
- measuring a period T of the signal directly or assigning value of period T of a predetermined signal;
- calculating DUTY by a following formula:
- DUTY=(.SIGMA.t.sub.ri +.SIGMA.t.sub.fi)/2T;
- and
- comparing DUTY with a specific maximum duty DUTYMAX of the logic element;
- wherein, if a comparison result is DUTY<DUTYMAX, it is judged that hot carriers have a small effect on the logic element and if the comparison result is DUTY>DUTYMAX, it is judged that hot carriers have a large effect on the logic element.
A method for checking the effects of hot carriers on a logic circuit, the logic circuit including a logic element coupled to a plurality of loads by a signal line, said method comprising steps of:
- measuring respective capacitances Ci and Cpi of the loads of the logic element;
- calculating total capacitance Cout (.SIGMA.Ci+.SIGMA.Cpi) of the plurality of loads;
- comparing said calculated Cout with maximum allowable capacitance Cmax;
- measuring t.sub.ri and t.sub.fi of a signal applied to the signal line;
- measuring total rising transition time .SIGMA.t.sub.ri ;
- measuring total falling transition time .SIGMA.t.sub.fi ;
- measuring a period T of the signal or assigning a value of period T of a predetermined signal;
- calculating DUTY by a following formula:
- DUTY=(.SIGMA.t.sub.ri !+.SIGMA.t.sub.fi !)/2T;
- comparing DUTY with a specific maximum duty DUTYMAX of the logic element;
- wherein, if a comparison result is DUTY<DUTYMAX, it is judged that hot carriers give a small effect on the logic element and if the comparison result is DUTY>DUTYMAX, it is judged that hot carriers give a large effect on the logic element.
Dependencies are inferred from the claim text.