Method and apparatus for improved video filter processing using efficient pixel register and data organization

A pixel register for a programmable video filter, the video filter including read and write address generators, a microcontroller and an array of processing elements, said pixel register comprising:

• a memory buffer for storing pixel values for filtering by the array of processing elements, said memory buffer comprising first and second memory banks each having a width corresponding to the number of processing elements, wherein a plurality of consecutive pixel values are stored in said memory buffer in two separate groups, including a first group of even pixel values stored in a first region of said memory buffer beginning in said first memory bank, and a second group of odd pixel values stored in a second region beginning in said second memory bank and separated from the beginning of said first region by an offset address value;
• select logic coupled to said memory buffer for selecting between respective columns of said first and second memory banks for retrieving pixel values according to a predetermined order;
• a shift network coupled to said select logic for reordering said accessed pixel values based on said address and for providing said reordered pixel values to the array of processing elements;
• and
• address decoder logic for decoding an address from an address generator for providing address values to said memory buffer, for providing a select value to said select logic and for providing a shift value to said shift network to retrieve pixel values from said first and second groups of pixel values.

A method for performing horizontal decimation on a plurality of consecutive pixel values by an n-element processing array, comprising the steps of:

• separating a plurality of pixel values into even and odd pixel values;
• storing said even and odd pixel values into two separate regions of two contiguous memory banks, including an even region for storing even pixel values beginning in one of the memory banks and an odd region for storing odd pixel values beginning in the other memory bank, each bank including n columns and a plurality of rows of data locations;
• retrieving a first set of even pixel values from the even region and providing the first set of pixel values to the processing array;
• retrieving a second set of associated odd pixel values from the odd region and providing the second set of pixel values to the processing array;
• and
• retrieving a third set of the next associated even pixel values from the even region and providing the third set of pixel values to the processing array.