Signal processing apparatus

A signal processing circuit for processing output signals from a CCD (charge-coupled device) imager of a multiple read-out type having horizontal and vertical blanking periods for receiving light signals from an iris and on which respective pilot signals are superimposed, comprising:

• a plurality of variable gain amplifiers for receiving said output signals from said CCD imager to produce respective amplified signals;
• a first loop circuit operable to adjust respective gains of said plurality of variable gain amplifiers;
• an iris control circuit operable to control said iris on the basis of said amplified signals;
• a second loop circuit operable at least once during each horizontal blanking period of said CCD image to similarly adjust said respective pilot signals at a desired level;
• a third loop circuit operable at least once during each horizontal blanking period of said CCD imager to equalize the levels of said respective pilot signals;
• and
• control means for controlling said first loop circuit, said iris control circuit, said second loop circuit, and said third loop circuit to operate during respective different time intervals in a predetermined cycle, said predetermined cycle being repeated at least once during each vertical blanking period of said CCD imager.