Display refresh system having reduced memory bandwidth
AssigneeAlliance Semiconductor Corporation
InventorsSpencer H. Greene, Andrew D. Daniel
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Abstract
A display refresh system (10) is disclosed wherein a display image is stored in a screen memory (12) as a number of screen rows (26) having consecutive addressable units. A redundancy memory (38) includes a redundancy row (48) corresponding to each screen row (26). Each redundancy row (48) stores run length data that indicates the number of identical consecutive addressable units within a screen row (26). Addressable units are written with accompanying run lengths to a FIFO (54). A register repeater (56) repeats the addressable unit at the FIFO output (62) a number of times equal to the run length. The run length is used to advance the refresh address to the next group of identical consecutive addressable units within the screen row (26).
Claims23
An improved computer graphics display refresh system, comprising:
- a screen memory for storing and manipulating a display image as a plurality of addressable units, the addressable units of the display image being arranged in a plurality of display rows;
- redundancy data means for providing a plurality of successive run lengths for each display row, the run lengths representing consecutive repetitions of identical addressable units in the display row;
- refresh address means for generating a refresh address, said refresh address means including an address advancer for advancing the refresh address in response to the run lengths of said redundancy data means;
- repeating FIFO means for receiving a plurality of consecutive addressable unit/run length pairs, said repeating FIFO means repeatedly outputting the value of the addressable unit in response to its accompanying run length;
- and
- a controller for writing the addressable unit at the refresh address and an accompanying run length to said repeating FIFO means.
In a graphics system wherein a display image is stored in a display memory as screen data in a plurality of screen rows, each screen row having a plurality of bits addressable as addressable units, the screen data being modified by a controller and the display image being periodically refreshed by writing the screen data to an output, a method of reducing the memory bandwidth consumed by the refresh operation, comprising the steps of:
- providing a redundancy data memory having a redundancy data row corresponding to each screen row;
- determining if a screen row has been modified since a previous recording of redundancy data;
- if the screen row has been modified, recording the redundancy data of consecutive addressable units to the redundancy data memory;
- and
- if the screen row has not been modified, beginning with the first addressable unit, generating a run length from the redundancy data, outputting the addressable unit a number of times corresponding to the run length, skipping subsequent addressable units according to the run length, selecting a next addressable unit and generating a next run length, and repeat this step until the end of the redundancy data row and the screen row is reached.
Dependencies are inferred from the claim text.