Spatial light modulator having redundant memory cells

A spatial light modulator, comprising;

• a) an array of picture elements;
• b) a plurality of primary memory cells associated with and controlling said picture elements;
• c) at least one spare memory cell;
• and
• d) memory cell formatting circuit means associated with said primary memory cells and said spare memory cells for selectively implementing one said spare memory cell in place of one said primary memory cell and functionally disabling said replaced primary memory cell, wherein said memory cell formatting circuit means comprises a network of fuses and a mapping circuit responsive to said network of fuses, said network of fuses comprising a series of fuses connected to ground on one end, and connected to a switch at the other end, said switch providing a potential to said series of fuses only when said spare memory cell is implemented, said series of fuses conducting substantially no current when said spare memory cells are not implemented.

A memory cell, comprising:

• a) a plurality of memory cells arranged in rows;
• b) memory cell addressing means for generating row address signals;
• and
• c) a mapping circuit coupled between said addressing means and said memory cell rows for selectively determining which subset of said memory cell rows are addressed by said row address signals, said mapping circuit having a separate logic cell associated with each said memory cell row, each said logic cell having two inputs receiving two of said row address signals and an output driving said associated memory cell row.

A memory cell array, comprising;

• a) an array of primary memory cells arranged in rows;
• b) at least one row of spare memory cells;
• and
• c) memory cell formatting circuit means associated with said primary memory cells and said spare memory cells for selectively implementing one said spare memory cell row in place of one said primary memory cell row and functionally disabling said replaced primary memory cell row, wherein said memory cell formatting circuit means comprises a mapping circuit responsive to a network of fuses, said network of fuses comprising a series of fuses connected to ground, on one end, and connected to a switch at the other end, said switch providing a potential to said series of fuses only when said spare memory cell is implemented, said series of fuses conducting substantially no current when said spare memory cells are not implemented.