Back to results
US 5,670,913 AGranted
Phase locked loop circuit with false locking detector and a lock acquisition sweep
AssigneeAlcatel
InventorFrancisco Manuel Garcia Palancar
Life of this patent
Estimating the term…
Loading patent…
Loading patent…
AssigneeAlcatel
InventorFrancisco Manuel Garcia Palancar
Estimating the term…
Based on a phase locked loop (PC1, CP1, VCXO) which receives an incoming data signal (DS) and generates a recovered clock signal (RC), in the event that this incoming data signal (DS) includes low frequency cycling, false phase locking can occur, consequently leading to impaired operation; in order to avoid this, according to the invention, there is also included a false locking detector (FLD) to which is applied the incoming data signal (DS) and the recovered clock signal (RC) and the output of, which is added in an adder circuit (ADD) to that coming from the first loop, for producing voltage pulses when both signals are not at the same frequency, provoking a non-locked state. Only when the frequency is correct, does the false locking detector (FLD) not alter loop operation.
Clock recovery circuit for an incoming data signal (DS) comprising a first phase locked loop (PC1, CP1, VCXO) comprising a first charge pump (CP1) having an output voltage which increases or decreases depending on output pulses from a first phase comparator (PC1), characterized in that a voltage-controlled oscillator (VCXO) of the first phase locked loop receives a signal coming from a false locking detector (FLD) which, in turn, receives the incoming data signal (DS) and a signal derived from an output of the voltage-controlled oscillator (VCXO), the false locking detector (FLD) comprising a second phase comparator (PC2) and a second charge pump (CP2) having an output signal for summation with said output voltage of the first charge pump (CP1) for control of the voltage-controlled oscillator (VCXO).
Dependencies are inferred from the claim text.