Semiconductor device having a boosting circuit

A semiconductor memory device, comprising:

• a memory cell array including a plurality of memory cells;
• a plurality of bit lines connected to respective memory cells;
• a plurality of word lines connected to respective memory cells;
• a bit decoder supplied with address data for selecting a bit line in response thereto;
• a word decoder supplied with address data for selecting a word line in response thereto;
• a boost circuit producing a boost voltage by boosting a supply voltage;
• and
• a boost control circuit supplied with said boost voltage and outputting said boost voltage to a load in response to a control signal, said boos control circuit comprising:
• a first transistor having a first diffusion region connected to said boost circuit and receiving the boost voltage produced thereby and a second diffusion region adapted for connection to said load for outputting said received boost voltage therefrom to said load, said first transistor being turned on when outputting said boost voltage from said second diffusion region to said load and turned off when interrupting output of said boost voltage from said second diffusion region to said load,
• a second transistor having a third electrode connected electrically to said second diffusion region of said first transistor and a fourth diffusion region, said second transistor being turned on irrespective of whether or not said first transistor is turned on, and
• a third transistor having a fifth electrode connected electrically to said fourth diffusion region of said second transistor and a sixth electrode connected electrically to a ground level, said third transistor being turned on when the output of said boost voltage from said second diffusion region to said load is interrupted and turned off when said boost voltage is output from said second diffusion region to said load, said second transistor having a conductance exceeding a conductance of said third transistor.

A boost control circuit, comprising:

• a first transistor having a first diffusion region connected to a boost circuit for receiving therefrom a boost voltage and a second diffusion region adapted for connection to a load for outputting said received boost voltage to said load, said first transistor being turned on when outputting said boost voltage from said second diffusion region to said load and turned off when interrupting output of said boost voltage from said second diffusion region to said load;
• a second transistor having a third electrode connected electrically to said second diffusion region of said first transistor and a fourth diffusion region, said second transistor being turned on irrespective of whether or not said first transistor is turned on;
• and
• a third transistor having a fifth electrode connected electrically to said fourth diffusion region of said second transistor and a sixth electrode connected electrically to a ground level, said third transistor being turned on when the output of said boost voltage from said second diffusion region to said load is interrupted and turned off when said boost voltage is output from said second diffusion region to said load, said second transistor having a conductance exceeding a conductance of said third transistor.

A semiconductor control circuit, comprising:

• a level conversion circuit supplied with an input signal for producing a first output signal with an amplitude larger than an amplitude of said input signal;
• and
• an inverter circuit comprising:
• a p-channel transistor and a first n-channel transistor connected in series thereto, said p-channel transistor and said first n-channel transistor having respective gates connected commonly to said level conversion circuit for receiving said first output signal therefrom, said p-channel transistor having a drain and outputting a second, inverted output signal from said drain, and
• a second n-channel transistor interposed between said drain of said p-channel transistor and said first n-channel transistor, said second n-channel transistor being turned on when said first n-channel transistor is turned on, said second n-channel transistor having a conductance exceeding a conductance of said first n-channel transistor.