Circuit for controlling output voltage from charge pump

A circuit for controlling output voltage from a charge pump, comprising:

• a charge pump to output a constant voltage through the output terminal based on command signals;
• a multi level selection decoder to output a plurality of pulse signals having different phases based on the command signals;
• a first voltage control circuit to generate a first positive voltage at said output terminal according to a first pulse signal from a multi level selection decoder, wherein said first voltage control circuit comprising a first NMOS transistor having a gate electrode, a drain region, a source region, a P.sup.+ -well and a N.sup.- -well, wherein said first NMOS transistor causes a breakdown effect to occur when output voltage from said charge pump is applied to the drain region, the source region is floated, a zero volt is applied to the P.sup.+ -well, and the gate electrode is grounded, a first means for supplying a first inverse signal to the P.sup.+ -well in said first NMOS transistor, wherein said first inverse signal is generated by inversion of the first pulse signal and a second means for supplying a VCC power supply to the source electrode of said first NMOS transistor based on the first pulse signal;
• a second voltage control circuit to generate a second positive voltage at said output terminal according to a second pulse signal from said multi level selection decoder, wherein said second voltage control circuit comprising a first transistor for high voltage coupled to the output terminal of said charge pump, said first transistor operating as a diode, a second NMOS transistor causes a breakdown effect to occur when the output voltage from said charge pump is applied to the drain region, the source region is floated, a zero volt is applied to the P.sup.+ -well, and the gate electrode is grounded, a third means for supplying a second inverse signal to the P.sup.+ -well in said second NMOS transistor, wherein the second inverse signal is generated by inversion of the second pulse signal and a fourth means for supplying a VCC power supply to the source electrode of said second NMOS transistor based on the second pulse signal;
• and
• a third voltage control circuit to generate a third positive voltage as said output terminal according to a third pulse signal from said multi level selection decoder, wherein said third voltage control circuit comprising a second transistor for high voltage coupled to the output terminal of said charge pump, wherein said second transistor is operated as diode, a third transistor for high voltage coupled to said second transistor, wherein said third transistor is operated as a diode, a third NMOS transistor having a gate electrode, a drain region, a source region, a P.sup.+ -well and a N.sup.- -well, wherein said third NMOS transistor causes a breakdown effect to occur when output voltage from said charge pump is applied to the drain region, the source region is floated, a zero volt is applied to the P.sup.+ -well, and the gate electrode is grounded, a fifth means for supplying a third inverse signal to the P.sup.+ -well in said third NMOS transistor, wherein the third inverse signal is generated by inversion of the third pulse signal and a sixth means for supplying a VCC power supply to the source electrode of said third NMOS transistor based on the third pulse signal.