Integrated circuit operable in a mode having extremely low power consumption

Abstract

An integrated circuit selectively operable in either a first mode (consuming low power) or a second mode (consuming relatively high power). The circuit includes MOS transistors and a supply voltage circuit for at least one of the transistors. In both modes, the supply voltage circuit holds the body of each transistor at a fixed voltage (e.g., a voltage V.sub.CC in a range from 5 to 5.5 volts, where each transistor is a PMOS device). In the second mode the supply voltage circuit supplies this fixed voltage to the source of each transistor, but in the first mode it supplies a voltage equal to or slightly offset from the fixed voltage to the source of each transistor. In some embodiments, the supply voltage circuit (in the first mode, after an initial transient state) supplies a first voltage to a well shared by a plurality of PMOS transistors, and a second voltage to the source of each PMOS device. Alternatively, the supply voltage circuit (in the first mode, after an initial transient state) supplies a first voltage to the body of each of a plurality of NMOS transistors, and a second voltage to the source of each NMOS device. The second voltage is preferably offset from the first voltage by a voltage drop chosen to achieve a desired decrease in transistor leakage current in the first mode and a desired power up time for a transition from the first mode to the second mode. In preferred embodiments, the integrated circuit is a memory chip including a flash memory array, the voltage drop is in the range from 1.4 volts to 2 volts, and the voltage drop is implemented with one diode-connected MOS transistor or two diode-connected MOS transistors connected in series.

Dependencies are inferred from the claim text.