Back to results
US 5,670,904 AGranted
Programmable digital delay unit
AssigneeSGS-Thomson Microelectronics S.A.
InventorsDavid Moloney, Paolo Gadducci
Life of this patent
Estimating the term…
Abstract
A programmable digital delay unit presenting a number of cascade-connected delay blocks, and a number of controlled bypass elements, one for each delay block. Each bypass element presents a bypass line and a multiplexer for selectively connecting the input or output of the respective delay block to the input of the next delay block. The delay blocks are formed by the cascade connection of flip-flops, and the number of flip-flops in each successive delay block, from the input of the delay unit, decreases in an arithmetic progression to the power of two, so that the selection signals for the respective multiplexers represent the bits of a digital word specifying the required delay.
Claims12
A programmable digital delay unit comprising:
- a plurality of delay blocks, each delay block having an input and an output, and including at least one delay element, each delay block operable to delay a digital input for a selected period of time;
- a plurality of multiplexers each connected to a corresponding one of the delay blocks, each multiplexer having first and second inputs respectively connected to the input and the output of the corresponding delay block, and an output connected to the input of a next delay block among the plurality of delay blocks;
- and
- means for disabling the at least one delay element of one delay block among the plurality of delay blocks to reduce power consumption.
1 more element
A programmable digital delay unit comprising:
- a plurality of delay blocks with each delay block including at least one delay element, each delay block having an input and an output, and being operable to delay a digital input for a selected period of time;
- a plurality of multiplexers each connected to a corresponding delay block among the plurality of delay blocks, each multiplexer having first and second inputs respectively connected to the input and the output of the corresponding delay block, the multiplexer having an output connected to the input of a next delay block among the plurality of delay blocks, each multiplexer selecting either the input or the output of the corresponding delay block as the input to the next delay block;
- and
- a delay element disable circuit connected to an input of the at least one delay element of one delay block among the plurality of delay blocks, the delay element disable circuit disabling the at least one delay element to reduce power consumption when the multiplexer corresponding to the one delay block connects the input of the one delay block to the input of the next delay block.
1 more element
A programmable digital delay unit comprising:
- a first delay block having an input and an output, and including at least one delay element;
- a first multiplexer having first and second inputs respectively connected to the input and the output of the first delay block to selectively bypass the first delay block;
- a second delay block including at least one delay element, the second delay block having an input connected to the output of the first multiplexer and an output;
- and
- a second multiplexer having first and second inputs respectively connected to the input and the output of the second delay block to selectively bypass the second delay block;
- and
- means for disabling at least one delay block of the first and second delay blocks to reduce power consumption when the at least one delay block is being bypassed.
4 more elements
A programmable digital delay unit comprising:
- a plurality of delay blocks, each delay block having an input and an output, and including at least one delay element, each delay block operable to delay a digital input for a selected period of time;
- a plurality of multiplexers each connected to a corresponding one of the delay blocks, each multiplexer having first and second inputs respectively connected to the input and the output of the corresponding delay block, the multiplexer having an output connected to the input of a next delay block among the plurality of delay blocks;
- and
- means for disabling the at least one delay element of one delay block among the plurality of delay blocks to reduce power consumption.
1 more element
A programmable digital delay unit comprising:
- a plurality of delay blocks, each delay block having an input and an output, and including at least one delay element, each delay block operable to delay a digital input for a selected period of time;
- a plurality of multiplexers each connected to a corresponding one of the delay blocks, each multiplexer having first and second inputs respectively connected to the input and the output of the corresponding delay block, the multiplexer having an output connected to the input of a next delay block among the plurality of delay blocks;
- and
- means, connected to a clock input of the at least one delay element of one delay block among the plurality of delay blocks, for isolating a clock signal from the clock input of the at least one delay element to reduce power consumption.
1 more element
A programmable digital delay unit comprising:
- a number of delay blocks, each presenting an input and an output;
- a number of controlled bypass elements, one for each delay block;
- each bypass element being connected to the input and to the output of the respective delay block for selectively connecting said input or said output of the respective delay block to the input of the next delay block;
- each said bypass element including a bypass line and a controlled switching element;
- each said bypass line being connected to the input of a respective delay block;
- and each switching element presenting two inputs connected respectively to the output of the respective delay block and to the respective bypass line, and an output connected to the input of the next delay block;
- and
- said delay unit having an input and an output, and further including general bypass means connected between said input and said output of said delay unit.
5 more elements
A programmable digital delay unit comprising:
- a number of delay blocks, each presenting an input and an output;
- a number of controlled bypass elements, one for each delay block;
- each bypass element being connected to the input and to the output of the respective delay block for selectively connecting said input or said output of the respective delay block to the input of the next delay block;
- each said bypass element including a bypass line and a controlled switching element;
- each said bypass line being connected to the input of a respective delay block;
- and each switching element presenting two inputs connected respectively to the output of the respective delay block and to the respective bypass line, and an output connected to the input of the next delay block;
- and
- delay block disabling means connected to at least one of the delay blocks.
5 more elements
Dependencies are inferred from the claim text.