Logic circuit controlled by a plurality of clock signals

A semiconductor integrated circuit comprising:

• a reference clock signal generation circuit that generates at least one reference clock signal;
• a clock signal delay device that successively delays the at least one reference clock signal to generate a plurality of delayed clock signals, each of the delayed clock signals having a phase that is shifted by a specified amount with respect to the other of the plurality of delayed clock signals;
• and
• a plurality of serially-connected circuit blocks defining a logic circuit to be controlled by the plurality of delayed clock signals,
• wherein each of the circuit blocks is controlled by a correspondingly one of the plurality of delayed clock signals, and
• the amount of phase shift between any two delayed clock signals that control adjacent circuit blocks is small enough to be substantially negligible with reject to a period of the reference clock signal so that the two delayed clock signals overlap.

A semiconductor integrated circuit comprising:

• a reference clock signal generation circuit that generates a data transfer reference clock signal and an operation reference clock signal;
• a plurality of first delay circuits that successively delays the data transfer reference clock signal to generate a plurality of delayed data transfer clock signals, each of the delayed data transfer clock signals having a phase that is shifted by a specified amount with respect to an adjacent delayed data transfer clock signal;
• a plurality of second delay circuits that successively delays the operation reference clock signal to generate a plurality of delayed operation clock signals, each of the delayed operation clock signals having a phase that is shifted by a specified amount with respect to an adjacent delayed operation clock signal;
• and
• a plurality of circuit blocks defining a logic circuit to be controlled by the data transfer clock signals and the operation clock signals,
• wherein one of the circuit blocks is controlled by the data transfer reference clock signal and the operation reference clock signal and each of the other circuit blocks is controlled by one of the plurality of delayed data transfer clock signals and one of the plurality of delayed operation clock signals.
• the data transfer reference clock signal overlaps with each of the delayed data transfer clock signals, and
• the operation reference clock signal overlaps with each of the delayed operation clock signals.

A method of operating a semiconductor integrated circuit having a logic circuit, the method comprising:

• dividing the logic circuit into N (N.gtoreq.2) serially-connected circuit blocks;
• and
• generating at least one reference clock signal;
• successively delaying the at least one reference clock signal to generate a plurality of delayed clock signals, each of the delayed clock signals having a phase that is shifted by a specified amount with respect to an adjacent delayed clock signal, the amount of phase shift between any two adjacent delayed clock signals being small enough to cause the two delayed clock signals to overlap;
• and
• controlling each of at least N-1 of the circuit blocks by one of the plurality of delayed clock signals.

A CMOS integrated circuit comprising:

• at least a CMOS gate;
• the CMOS gate including an input terminal, an output terminal, a PMOS transistor with a gate, an NMOS transistor with a gate, and a latch circuit for transferring data to the input terminal by clock signal control, wherein the gates of the PMOS transistor and the NMOS transistor are commonly connected to the input terminal;
• an auxiliary PMOS transistor inserted between the PMOS transistor and the output terminal;
• an auxiliary NMOS transistor inserted between the NMOS transistor and the output terminal;
• and
• a timing control circuit that maintains the auxiliary PMOS transistor and the auxiliary NMOS transistor in an OFF state during a specified period of time in which an electric potential output of the CMOS gate is in transition.

A method of operating a CMOS integrated circuit, the method comprising the steps of:

• providing at least one CMOS gate;
• the CMOS gate including an input terminal, an output terminal, a PMOS transistor with a gate, an NMOS transistor with a gate, and a latch circuit for transferring data to the input terminal by clock signal control, wherein the gates of the PMOS transistor and the NMOS transistor are commonly connected to the input terminal;
• inserting an auxiliary PMOS transistor between the PMOS transistor and the output terminal;
• inserting an auxiliary NMOS transistor between the NMOS transistor and the output terminal;
• and
• maintaining the auxiliary PMOS transistor and the auxiliary NMOS transistor in an OFF state during a specified period of time in which an electric potential output of the CMOS gate is in transition by using a reference clock signal.

A semiconductor integrated circuit comprising:

• a reference clock signal generation circuit that generates at least one reference clock signal;
• a clock signal delay device that delays the reference clock signal to generate a plurality of delayed clock signals, the plurality of delayed clock signals including a first delayed clock signal and a second delayed clock signals;
• and
• a plurality of circuit blocks defining a logic circuit to be controlled by clock signals, the plurality of circuit blocks including a first circuit block, a second circuit book, and a third circuit block,
• wherein the first circuit block is controlled by the reference clock signal, the second circuit block is controlled by the first delayed clock signal, and the third circuit block is controlled by the second delayed clock signal,
• the amount of delay between the reference clock signal and the first delayed clock signal is so small as to cause the reference clock signal to overlap with the first delayed clock signal, and
• the amount of delay between the first delayed clock signal and the second delayed clock signal is so small as to cause the first delayed clock signal to overlap with the second delayed clock signal.

A semiconductor integrated circuit comprising:

• a reference clock signal generation circuit that generates at least one reference clock signal;
• a clock signal delay device that delays the reference clock signal to generate a plurality of delayed clock signals, the plurality of delayed clock signals including a first delayed clock signal and a second delayed clock signals, the first delayed clock signal having a phase that is shifted by a specified amount with respect to the reference clock signal and the second delayed clock signal having a phase that is shifted by a specified amount with respect to the first delayed clock signal;
• and
• a plurality of circuit blocks defining a logic circuit to be controlled by clock signals, the plurality of circuit blocks including a first circuit block, a second circuit bock, and a third circuit block,
• wherein the first circuit block is controlled by the reference clock signal, the second circuit block is controlled by the first delayed clock signal, and the third circuit block is controlled by the second delayed clock signal,
• the reference clock signal substantially overlaps the first delayed clock signal, and
• the first delayed clock signal substantially overlaps with the second delayed clock signal.

A CMOS integrated circuit comprising:

• at least a CMOS gate, the CMOS gate including an input terminal, an output terminal, a PMOS transistor with a gate, an NMOS transistor with a gate, and a latch circuit for transferring data to the input terminal by clock signal control, wherein the gates of the PMOS transistor and the NMOS transistor are commonly connected to the input terminal;
• at least one of an auxiliary PMOS transistor connected in series with the PMOS transistor and an auxiliary NMOS transistor connected in series with the NMOS transistor;
• and
• a timing control circuit that maintains the at least one of the auxiliary PMOS transistor and the auxiliary NMOS transistor in an OFF state during a specified period of time in which an electric potential at the input terminal of the CMOS gate is in transition.