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US 5,670,898 AGranted
Low-power, compact digital logic topology that facilitates large fan-in and high-speed circuit performance
AssigneeSilicon Graphics, Inc.
InventorEmerson Fang
Life of this patent
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Abstract
A circuit topology for implementing combinational logic functions with large fan-in, high speed, and low power consumption using a combination of dynamic and static gates. The circuit topology includes a dynamic gate and a Pseudo-NMOS gate coupled to the dynamic gate.
Claims4
A circuit topology for implementing combinational logic functions comprising:
- a dynamically precharged gate;
- and
- a Pseudo-NMOS gate coupled to said dynamically precharged gate, comprising
- an active load;
- a switch coupled to said active load;
- and
- a power control circuitry comprising
- a second active load coupled to said first active load;
- and
- a second switch coupled to said second active load.
7 more elements
Dependencies are inferred from the claim text.