Semiconductor device having output signal control circuit

A semiconductor circuit comprising:

• an input means;
• an output means including a transistor;
• and
• a control signal control means disposed between said input means and output means, which outputs a control voltage for use in driving said transistor in said output means, wherein said control signal control means responds to a transition of a signal fed to said input means and changes said control signal at a lower temporal coefficient of variation of said control signal during a time interval (second time interval), from when said control signal reaches a threshold voltage of said transistor in said output means until the output signal of said output transistor stops changing, than during a preceding time interval (first time interval) or a succeeding time interval (third time interval), and wherein said control signal control means includes a first control circuit that, when a signal fed to said input means makes a high-to-low transition, changes the temporal coefficient of variation of said control signal, and a second control circuit that, when said signal fed to said input means makes a low-to-high transition, changes said temporal coefficient of variation of said control signal, and wherein said second control circuit includes a first p-channel transistor having a gate thereof connected to said first terminal, a first source or drain thereof being connected to a fifth terminal, and a second source or drain being connected to said third terminal, a second p-channel transistor having a gate thereof connected to a sixth terminal, a first source or drain thereof being connected to a high-voltage line V.sub.DD 2, and a second source or drain thereof being connected to said fifth terminal, a third p-channel transistor having a gate thereof connected to a seventh terminal, a first source or drain thereof being connected to a high-voltage line V.sub.DD 3, and a second source or drain thereof being connected to said fifth terminal, a dual-input NAND gate circuit NAND having a first input terminal thereof connected to said input terminal, a second input terminal thereof being connected to said third terminal , and an output terminal thereof being connected to an eighth terminal, a fourth p-channel transistor having a gate thereof connected to said eighth terminal, a first source or drain thereof being connected to a high-voltage line V.sub.DD 4, and a second source or drain thereof being connected to said third terminal, and an intermediate-voltage generator means 6 having an input terminal thereof connected to said first terminal, a first output terminal thereof being connected to said sixth terminal, and a second output terminal thereof being connected to said seventh terminal, and having a voltage at said first output terminal set to be higher than the one at said second output terminal.

A semiconductor circuit, comprising:

• an output transistor connected between an output node and a reference voltage;
• an inverter connected between an input node and a gate of the output transistor;
• and
• a first variable resistor circuit connected between the reference voltage and a power node of the inverter;
• a second variable resistor circuit connected between the gate of the output transistor and the reference voltage, and a resistance value thereof being set in such a way that the resistance value after completion of a change of the potential of the output node becomes a value smaller than the resistance value just before completion of the change;
• wherein a resistance value of the first variable resistor circuit is set in such a way that the resistance value, during a term from when a gate potential of the output transistor reaches to approximately the same value as a threshold value of the output transistor in response to the change of the potential of the input node until the change of the potential of the output node is completed, is set to a resistance value larger than the resistance value just before the term.

A semiconductor circuit, comprising:

• an output transistor connected between an output node and a reference voltage;
• an inverter connected between an input node and a gate of the output transistor;
• and
• a first variable resistor circuit connected between a power line and a power node of the inverter;
• a second variable resistor circuit connected between the gate of the output transistor and the power line, and a resistance value thereof being set in such a way that the resistance value after completion of a change of the potential of the output node becomes a value smaller than the resistance value just before completion of the change;
• wherein a resistance value of the first variable resistor circuit is set in such a way that the resistance value, during a term from when a gate potential of the output transistor reaches to approximately the same value as a threshold value of the output transistor in response to the change of the potential of the input node until the change of the potential of the output node is completed, is set to a resistance value larger than the resistance value just before the term.