BiCMOS logic circuit with bipolar base clamping

A BiCMOS logic gate circuitry comprising:

• an input terminal for receiving input logic signals having a high level which is the same as a power source;
• an output terminal connected to an external load for permitting output logic signals to be outputted;
• a CMOS circuit having an input side which is connected to said input terminal for receiving said input signals and having an output side from which clamping-free logic signals are outputted;
• an output pull-up bipolar transistor connected in series between a high voltage line and said output terminal, said output pull-up bipolar transistor having a base which is connected to an output side of said CMOS circuit for allowing said output pull-up bipolar transistor to be driven by said clamping-free logic signals;
• an output pull-down bipolar transistor connected in series between a low voltage line and said output terminal so as to form a series connection of said output pull-up and output pull-down bipolar transistors between said high and low voltage lines, said output pull-down bipolar transistor having a base connected to said CMOS circuit so that said CMOS circuit is biased between said high voltage line and said base of said output pull-down bipolar transistor;
• a clamping circuit biased between said high and low voltage lines, said clamping circuit having a clamping terminal which is connected to said base of said output pull-down bipolar transistor for clamping a base potential of said output pull-down bipolar transistor which is lower than a threshold potential level at which said output pull-down bipolar transistor turns ON and OFF and which is higher than ground voltage, and said clamping circuit further having a higher impedance that an input impedance of said base of said output pull-down bipolar transistor;
• and
• an n-channel MOS field effect transistor having a gate which is connected to said input terminal for receiving said input logic signals, said n-channel MOS field effect transistor being connected in series between said output terminal and said base of said output pull-down bipolar transistor for clamping a low level of said output logic signals appearing on said output terminal to said base potential clamped by said clamping circuit to thereby prevent said output pull-down bipolar transistor from entering into a saturation state.