Integrated circuit interlevel conductor defect characterization test structure and system
AssigneeAnalog Devices, Inc.
InventorsGeoff O'Donoghue, Scott C. Munroe
Life of this patent
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Abstract
An interlevel conductor defect characterization integrated circuit test structure including first and second spaced test pads, a conductor layer, an insulator layer between the conductor layer and the test pads; and a first interlevel conductor having a unit cross-sectional conductive area extending between the first test pad and the conductor layer, and a second interlevel conductor extending between said second test pad and said conductor layer and having a cross-sectional conductive area substantially greater than the unit area for detecting defects which restrict the current carrying capacity of said unit area of the first interlevel conductor but not the second interlevel conductor.
Claims6
An interlevel conductor defect characterization integrated circuit test structure comprising:
- first and second spaced test pads;
- a conductor layer;
- an insulator layer between said conductor layer and said test pads;
- and
- a first interlevel unit conductor having a unit cross-sectional conductive area extending between said first test pad and said conductor layer, and a second interlevel conductor extending between said second test pad and said conductor layer and having a cross-sectional conductive area substantially greater than said unit area for detecting defects which restrict the current carrying capacity of said unit area of said first interlevel conductor but not said second interlevel conductor.
An integrated circuit interlevel conductor defect characterization test structure system comprising:
- a plurality of test structures each including:
- first and second spaced test pads;
- a conductor layer;
- an insulator layer between said conductor layer and said test pads;
- and
- a first interlevel unit conductor having a unit cross-sectional conductive area extending between said first test pad and said conductor layer, and a second interlevel conductor extending between said second test pad and said conductor layer and having a cross-sectional conductive area substantially greater than said unit area for detecting defects which restrict the current carrying capacity of said unit area of said first interlevel conductor but not said second interlevel conductor.
Dependencies are inferred from the claim text.