Regulated complementary charge pump with imbalanced current regulation and symmetrical input capacitance
AssigneeSun Microsystems, Inc.
InventorRobert J. Weisenbach
Life of this patent
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Abstract
A CMOS regulated complementary charge pump circuit uses imbalanced current regulation and symmetrical capacitive loading of input signals to provide a proportional response and high sensitivity at small phase differences. The charge pump is suitable for operation at very high frequencies, and therefore finds applications in delay-locked and phase-locked loops used to regenerate system clock signals within VLSI circuits. The use of current limiting devices in the switch pass gates permits a balancing of the capacitive loads presented to the input signals. Adjustable capacitors permit the elimination of a static phase offset at a zero operating point.
Claims17
A charge pump circuit, comprising:
- an output line for supplying a regulated current in proportion to a duration of a first input pulse, and for sinking a regulated current in proportion to a duration of a second input pulse;
- inverting means for providing inverses of the first and second input pulses;
- current regulators defining a current source and a current sink;
- a first pair of complementary pass transistors responsive to the first input pulse and its inverse for connecting the current source to the output line;
- a second pair of complementary pass transistors responsive to the second input pulse and its inverse for connecting the current sink to the output line;
- fixed bias means for reducing the current through each pass transistor;
- and
- regulated means, responsive to the output line, for reducing the current through one pass transistor relative to the other pass transistor of each complementary pair.
A method for operating a charge pump to minimize phase jitter at very small phase-differences, the method comprising the steps of:
- providing a regulated current source and a regulated current sink;
- providing input lines for receiving first and second digital control pulses;
- providing an output line;
- providing inverters for inverting the first and second pulses;
- providing a first pair of complementary pass transistors responsive to the first pulse and its inverse for connecting the current source to the output line;
- providing a second pair of complementary pass transistors responsive to the second pulse and its inverse for connecting the current sink to the output line;
- providing regulated means, responsive to the output line, for reducing the current through one pass transistor relative to the other pass transistor of each complementary pair;
- reducing the current through one pass transistor relative to the other pass transistor of each complementary pair in proportion to a voltage level on the output line;
- using the first pair of complementary pass transistors to connect the current source to the output line in response to the first pulse and its inverse;
- and
- using the second pair of complementary pass transistors to connect the current sink to the output line in response to the second pulse and its inverse.
A controlled loop for frequency and phase locking a local clock signal to a system reference signal, the loop comprising:
- an input line for receiving the system reference signal;
- an output line for providing the local clock signal;
- a phase-frequency detector circuit connected to receive the input signal and the output signal and providing first and second digital control signals;
- a charge pump circuit defining a constant current source and a constant current sink and including complementary pass transistors for connecting the current source to an output line while the first digital control signal is active and for connecting the current sink to the output line while the second digital control signal is active, and regulating means responsive to the output line for imbalancing the current through complementary pass transistors;
- a filter circuit connected to receive the charge pump output line and providing an analog control voltage output signal;
- a voltage-controlled device having one input connected to receive the analog control voltage, and an output line for supplying the local clock signal,
- whereby a frequency and phase locked loop is formed.
Dependencies are inferred from the claim text.