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US 5,670,829 AGranted
Precision current limit circuit
AssigneeMotorola, Inc.
InventorDavid M. Susak
Life of this patent
Estimating the term…
Abstract
A current limit circuit (10) uses a reference current (28) with zero temperature coefficient. A feedback loop (18, 26, 22) maintains substantially equal V.sub.GS for first (22) and second (24) transistors. The reference current sets the current through the first transistor which therefore limits the current in the second transistor. The second transistor is a power device that supplies current to a squib detonation device (38) in automotive air bag application.
Claims19
A current limit circuit, comprising:
- a first current source;
- a first transistor having a gate coupled to a first node, and a drain and source conduction path coupled to an output of said first current source;
- a second transistor having a gate coupled to said first node, a drain coupled to a first terminal, and a source coupled to a second terminal;
- and
- a feedback circuit coupled between said sources of said first and second transistors and said first node to maintain substantially equal gate-source voltages for said first and second transistors, said feedback circuit including,
- (a) a second current source,
- (b) a third transistor having a collector coupled to a first output of said second current source at said first node, and an emitter coupled to said second terminal, and
- (c) a fourth transistor having a collector and base coupled together to a second output of said second current source and to a base of said third transistor, and an emitter coupled to said output of said first current source.
5 more elements
A current limit circuit, comprising:
- a first current source;
- a first transistor having a gate coupled to a first node, and a drain and source conduction path coupled to an output of said first current source;
- a second transistor having a gate coupled to said first node, a drain coupled to first terminal, and a source coupled to a second terminal;
- and
- a feedback circuit coupled between said sources of said first and second transistors and said first node to maintain substantially equal gate-source voltages for said first and second transistors, said feedback circuit including,
- (a) a second current source,
- (b) a third transistor having a collector and base coupled together to an output of said second current source at said first node, and
- a fourth transistor having a collector coupled to an emitter of said third transistor at a second node, an emitter coupled to said second terminal, and a base coupled to said output of said first current source.
5 more elements
In a squib control integrated circuit, a current limit circuit, comprising:
- first and second current sources;
- a first transistor having a collector coupled to a first output of said first current source at a first node, and an emitter coupled to a first terminal;
- a second transistor having a collector and base coupled together to a second output of said first current source and to a base of said first transistor, and an emitter coupled to an output of said second current source;
- a third transistor having a gate coupled to said first node, and a drain and source conduction path coupled to said output of said second current source;
- and
- a fourth transistor having a drain coupled to a second terminal, a gate coupled to said first node, and a source coupled to said first terminal.
3 more elements
A current limit circuit, comprising:
- first and second current sources;
- a first transistor having a collector and base coupled together to an output of said first current source at a first node;
- a second transistor having a collector coupled to an emitter of said first transistor at a second node, an emitter coupled to a first terminal, and a base coupled to an output of said second current source;
- a third transistor having a gate coupled to said first node, and a drain and source conduction path coupled to said output of said second current source;
- and
- a fourth transistor having a drain coupled to a second terminal, a gate coupled to said second node, and a source coupled to said first terminal.
3 more elements
Dependencies are inferred from the claim text.