Field effect transistor having contact layer of transistor gate electrode material
AssigneeInternational Business Machines Corporation
InventorsEric Adler, Subhash Balakrishna Kulkarni, Randy William Mann, Werner Alois Rausch, Luigi Ternullo, Jr.
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Abstract
Improved field effect transistor (FET) structures are described. They include a thin film transistor (TFT), wherein a contact layer directly connects a diffusion region of the TFT to an active site of another device, e.g., another transistor. This invention is especially suitable for TFT's which are built on one or more conductive studs. Static random access memory (SRAM) cells incorporating one or more of the TFT's are also described. Moreover, this invention is directed to methods for preventing or alleviating the problems associated with gouging during formation of contact layers.
Claims21
A field effect transistor (FET) structure, comprising:
- a) a thin film transistor which itself comprises a diffusion region and a channel;
- a gate dielectric layer disposed over the channel and a first portion of the diffusion region;
- and a transistor gate electrode disposed over a portion of the gate dielectric layer, and substantially self-aligned with the channel;
- b) a stud underlying and connected to the thin film transistor;
- and
- c) a contact layer of transistor gate electrode-material applied over at least a portion of the diffusion region;
- wherein the contact layer is formed simultaneously with the transistor gate electrode.
An FET structure, comprising:
- a) a thin film transistor which itself comprises a diffusion region and a channel;
- a gate dielectric layer disposed over the channel and a first portion of the diffusion region;
- and a transistor gate electrode disposed over a portion of the gate dielectric layer, and substantially self-aligned with the channel;
- b) at least one stud underlying the thin film transistor, and connected to a second portion of the diffudion rregion;
- wherein the stud has an expanded width, such that a portion of the stud is disposed under a portion of the gate dielectric layer;
- and
- c) a contact layer of transistor gate electrode material applied over at least some of the second portion of the diffusion region;
- wherein the contact layer is formed simultaneously with the transistor gate electrode.
Dependencies are inferred from the claim text.