Three-dimensional SRAM trench structure and fabrication method therefor

A semiconductor trench structure comprising:

• a substrate having a plurality of layers thereon;
• a first semiconductor device including a first input and a first output, said first semiconductor device being formed on said substrate in said plurality of layers;
• a second semiconductor device including a second input and a second output, said second semiconductor device being formed on said substrate in said plurality of layers substantially adjacent to said first semiconductor device;
• a trench formed in the plurality of layers to intersect said first semiconductor device and said second semiconductor device, said first semiconductor device and said second semiconductor device being disposed at a first sidewall of said trench;
• means for electrical connection disposed within said trench, said means for electrical connection being electrically connected to said first semiconductor device and said second semiconductor device such that said first input and said second output are electrically coupled within said trench and said first output and said second input are electrically coupled within said trench, thereby electrically cross-coupling said first semiconductor device and said second semiconductor device;
• and
• further comprising a third semiconductor device including a third input and a third output, said third semiconductor device being intersected by the trench, and a fourth semiconductor device including a fourth input and a fourth output, said fourth semiconductor device being intersected by the trench, and wherein said third input and said fourth output are electrically coupled within the trench and said third output and said fourth input are electrically coupled within the trench by said means for electrical connection, thereby electrically cross-coupling said third semiconductor device and said fourth semiconductor device, and wherein said means for electrical connection couples said first output and said third output to said second input and said fourth input, and couples said second output and said fourth output to said first input and said third input.

An SRAM cell comprising:

• a semiconductor structure having a trench disposed therein, said trench extending along an axis substantially orthogonal to a top surface of said semiconductor structure;
• a first inverter formed in said semiconductor structure adjacent to a first location in said trench along said axis;
• a second inverter formed in said semiconductor structure adjacent to a second location in said trench along said axis;
• means for electrical cross-coupling disposed within said trench, wherein said first inverter and said second inverter are electrically cross-coupled by said means for electrical cross-coupling such that an output of the first inverter is electrically connected to an input of the second inverter and an input of the first inverter is electrically connected to an output of the second inverter wherein said first inverter and said second inverter comprise a flip-flop;
• and
• an I/O transistor formed in said semiconductor structure, said I/O transistor being electrically connected to said means for electrical cross-coupling for facilitating writing to and reading from said SRAM cell.