US 5,670,423 AGranted

Method for using disposable hard mask for gate critical dimension control

AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.

InventorChue-San Yoo

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Abstract

A new method of controlling the critical dimension width of polysilicon by using a disposable hard mask is described. A semiconductor substrate is provided wherein the surface of the substrate has an uneven topography. A layer of polysilicon is deposited over the uneven surface of the substrate. The polysilicon layer is covered with a spin-on-glass layer wherein the spin-on-glass material planarizes the surface of the underlying topography. A semiconductor layer is deposited over the surface of the planarization layer to act as a hard mask wherein the semiconductor layer is opaque to actinic light. The semiconductor layer is covered with a uniform thickness layer of photoresist. The photoresist layer is exposed to actinic light wherein the semiconductor layer prevents reflection of the actinic light from its surface. The photoresist layer is developed and patterned to form the desired photoresist mask for the polysilicon layer. The semiconductor layer, the spin-on-glass layer, and the polysilicon layer not covered by the photoresist mask are anisotropically etched away to form polysilicon gate electrodes and interconnection lines. The photoresist mask, the hard mask, and the spin-on-glass layer are removed to complete the formation of polysilicon gate electrodes and interconnection lines having uniform critical dimension in the fabrication of an integrated circuit.

Claims10

Dependent claims

A method of providing a uniform critical dimension of gate electrodes and interconnection lines during etching in the fabrication of an integrated circuit comprising:

providing field oxide isolation areas surrounding bare active areas in and on a semiconductor substrate wherein the surface of said substrate has an uneventopography;
growing a gate silicon oxide layer on the surface of said field oxide areas and said active areas of said semiconductor substrate;
depositing a conducting layer over said gate silicon oxide layer;
covering said conducting layer with a spin-on-glass layer wherein said spin-on-glass layer planarizes the surface of said substrate;
depositing a titanium layer over the surface of said spin-on-glass layer wherein said titanium layer is opaque to actinic light;
covering said titanium layer with a uniform thickness layer of photoresist;
exposing said photoresist layer to actinic light wherein said titanium layer prevents reflection of said actinic light from its surface and developing and patterning said photoresist layer to form a photoresist mask for said conducting layer;
anisotropically etching away said titanium layer, said spin-on-glass layer, and said conducting layer not covered by said photoresist mask to form said gate electrodes and interconnection lines wherein the width of said gate electrodes and interconnection lines is said critical dimension;
and
removing said photoresist mask, remaining said titanium layer, and remaining said spin-on-glass layer to complete the formation of said gate electrodes and interconnection lines having said uniform critical dimension in the fabrication of said integrated circuit.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 08/663,431Filed 13 Jun 1996 · division
Priority: 5 May 1995
Granted: 23 Sep 1997
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

H10W 10/012
Of isolation regions comprising dielectric materials: using local oxidation of silicon [LOCOS]
H10D 64/01326
Characterised by the conductor: aspects related to lithography, isolation or planarisation of the conductor
H10P 50/71
Etching of wafers, substrates or parts of devices: using masks for conductive or resistive materials
H10W 10/13
Isolation regions comprising dielectric materials: formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation…