Method of fabricating antifuses in an integrated circuit device and resulting structure
AssigneeCrosspoint Solutions, Inc.
InventorsPankaj Dixit, William P. Ingram, III, Monta R. Holzworth, Richard Klein
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Abstract
Various improvements in the fabrication of an antifuse having silicon-amorphous silicon-metal layer structure are presented. Included are improved deposition techniques for the amorphous silicon layer. The improvements include steps for the fabrication of such an antifuse without the use of platinum and the resulting antifuse and contact structures.
Claims7
In a method of fabricating antifuses in an integrated circuit including the step of depositing a layer of amorphous silicon, an improvement comprising
- depositing said amorphous silicon layer in a process chamber having a low-pressure atmosphere with essentially no nitrogen, said atmosphere lower than ambient;
- removing said atmosphere from said chamber at a rate of no more than 2 millitorr per minute;
- whereby the avoidance of silicon nitride deposition in said amorphous silicon layer is enhanced.
In a method of fabricating antifuses in an integrated circuit including the step of depositing a layer of amorphous silicon, an improvement comprising
- depositing said amorphous silicon in a process chamber by plasma-enhanced chemical vapor deposition at a temperature in the range of 300.degree.-400.degree. C.;
- and
- running a mixture of argon and 5-10% silane through said process chamber at a flow rate of 4000 sccm for argon and at a flow rate of 200-400 sccm for silane.
In a method of fabricating antifuses in an integrated circuit including the step of depositing a layer of amorphous silicon, an improvement comprising
- depositing said amorphous silicon in a process chamber by plasma-enhanced chemical vapor deposition at a temperature in the range of 300.degree.-400.degree. C. and at a pressure in the range of 2-6 Torr.
Dependencies are inferred from the claim text.