Field emission device cathode and method of fabrication
AssigneeTexas Instruments Incorporated
InventorEdward C. Lee
Life of this patent
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Abstract
A microtip of a field emission device cathode (10) may be fabricated by forming a dielectric layer (18) on an upper surface of a resistive layer (16). A gate layer (20) is formed on the dielectric layer (18). An opening is formed in the gate layer (20) and a microtip cavity (28) is formed in the dielectric layer (18). The microtip cavity (28) extends through the opening in the gate layer (20) to the resistive layer (16). Layers of metal are formed on the gate layer (20) and the resistive layer (16) such that a microtip (30) is formed within the microtip cavity (28). Finally, polishing is performed to remove a portion of the overburden or layers of metal on the gate layer (20). The polishing continues until the microtip (30) is exposed.
Claims16
A method for fabricating a microtip of a field emission device cathode, comprising the steps of:
- forming a dielectric layer, having an upper surface and a lower surface, on a resistive layer;
- forming a gate layer on the dielectric layer;
- forming an opening in the gate layer;
- forming a microtip cavity in the dielectric layer through the opening in the gate layer that extends to the resistive layer;
- forming a layer of metal on the gate layer and on the resistive layer to produce a microtip on the resistive layer within the microtip cavity;
- and
- polishing off the layer of metal on the gate layer, until the microtip is exposed.
A method for fabricating a microtip of a field emission device cathode, comprising the steps of:
- forming a dielectric layer, having an upper surface and a lower surface, on a resistive layer;
- forming a microtip cavity in the dielectric layer that extends from the upper surface to the lower surface of the dielectric layer exposing the resistive layer;
- forming a layer of metal on the dielectric layer and the resistive layer to produce a microtip on the resistive layer within the microtip cavity, the layer of metal on the dielectric layer creating a gate layer having an opening over the microtip cavity;
- and
- polishing the layer of metal with chemical mechanical planarization until the microtip is exposed.
Dependencies are inferred from the claim text.