System and method having processor with selectable burst or no-burst write back mode depending upon signal indicating the system is configured to accept bit width larger than the bus width
AssigneeIntel Corporation
InventorsSundaravarathan R. Iyengar, Mustafiz R. Choudhury
Life of this patent
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Abstract
A processor for processing information is described. The processor can select between a write-burst mode of transferring information and an individual write cycle mode of transferring information. The write-burst mode of transferring information is a transfer of information in a single burst transaction and the individual write cycle mode of transferring information is a transfer of information in separate write cycles.
Claims5
A computer system comprising:
- a bus having a first bit width;
- a processor coupled to said bus, the processor having a selector unit that selects either a write-burst mode or a non-burst mode of transferring information from the processor to the external memory for a write-back cycle;
- an external device coupled to the bus that transmits a first signal which indicates that the computer system is configured to accept write cycle having a second bit width larger than the first bit width;
- and
- the processor further having a pin coupled to receive the first signal from the external device, wherein the selector unit selects the write-burst mode responsive to the first signal;
- otherwise the selector unit selects the non-write burst mode.
A method of transferring information from a processor to an external memory during a write-back cycle, the processor operating in either a write-burst mode or a non-burst mode of transferring information, the method including the steps of:
- transmitting a first signal to the processor from a first device external to the processor, the first signal indicating that a computer system, incorporating the processor and the first external device, is configured to accept a write cycle having a bit width larger than the bit width of a bus coupling the processor and the external memory;
- receiving the first signal at the processor via a pin;
- and
- responsive to the first signal, selecting the write-burst mode for the transfer of information from the processor to the external memory of the computer system during the write-back cycle.
Dependencies are inferred from the claim text.