System for transferring M elements X times and transferring N elements one time for an array that is X*M+N long responsive to vector type instructions

A computer system comprising:

• memory means for storing vector data comprising arrays of data elements;
• a processing unit operating upon the vector data stored in the memory means one element at a time;
• a plurality of addressable vector registers connected between the memory means and the processing unit to transfer arrays of vector data therebetween, each vector register having a depth of a plurality of elements;
• first means for transferring vector data between one or more of the vector registers and the processing unit to operate upon the vector data in the processing unit in the foreground;
• second means for transferring vector data between one or more of the vector registers and the memory means concurrently with the first means to make available vector data in the background;
• means for controlling the vector registers to sequence the transfer of vector data between the memory means and the processing unit to occur one element at a time until an entire array has been processed;
• a plurality of addressable scalar registers for storing data during operation of the processing unit;
• means for mapping to each vector and scalar register an address applicable to both the scalar and vector instructions;
• and
• means for accessing the registers during execution of the scalar and vector instructions.

A computer system comprising:

• memory means for storing vector data comprising arrays of data elements;
• a processing unit operating upon the vector data stored in the memory means one element at a time;
• first, second, and third vector registers connected between the memory means and the processing unit to transfer arrays of vector data therebetween, each vector register having a depth of a plurality of elements;
• means for first transferring unprocessed vector data from the first register to the processing unit;
• means for second transferring processed vector data from the processing unit to the second register after the first transfer;
• means for third transferring processed vector data from the second register and unprocessed vector data from the third register to the processing unit after the second transfer;
• means for fourth transferring processed vector data from the processing unit to one of the registers other than the third register after the third transfer;
• and
• means for controlling the vector registers to sequence the transfer of vector data between the memory means and the processing unit to occur one element at a time until the entire arrays have been processed.

A computer system comprising:

• memory means for storing vector data comprising arrays of data elements;
• a processing unit operating upon the vector data stored in the memory means one element at a time;
• first and second vector registers connected between the memory means and the processing unit to transfer arrays of vector data therebetween, each vector register having a depth of a plurality of elements;
• means for first transferring unprocessed vector data from the first register to the processing unit;
• means for second transferring processed vector data from the processing unit to the second register after the first transfer;
• means for third transferring processed vector data from the second register to the processing unit after the second transfer;
• means for fourth transferring processed vector data from the processing unit to one of the registers other than the second register after the third transfer;
• and
• means for controlling the vector registers to sequence the transfer of vector data between the memory means and the processing unit to occur one element at a time until the entire arrays have been processed.

A computer system for executing scalar type instructions having data elements as operands and vector type instructions having data elements and arrays of data elements as operands, scalar type instructions and vector type instructions each having an instruction type designating field and an operand register designating field, the instructions and data elements being stored in a main memory, comprising:

• a plurality of scalar registers identified by addresses stored in the operand register designating field of the instructions, each scalar register having a depth of one data element;
• a plurality of vector registers identified by the same addresses as some of the scalar registers, such addresses being stored in the operand register designating field of the instructions wherein the plurality of vector registers are visible in the scalar register address space, each vector register having a depth of a plurality of data elements;
• processing means for executing the scalar type instructions and the vector type instructions, said processing unit including
• means for decoding the instruction type designating field and the operand register designating field of each instruction to select at least one scalar register as an operand if the instruction is a scalar type instruction and to select at least one vector register if the instruction is a vector type instruction, and
• means for storing intermediate processing results of vector type instructions in selected ones of the plurality of vector registers;
• bus control means coupled to the main memory, the plurality of scalar registers, and the plurality of vector registers for transferring data elements between the plurality of scalar registers and the main memory, and for transferring entire arrays of data elements between the plurality of vector registers and the main memory, wherein data transfers to and from the plurality of scalar registers and to and from the plurality of vector registers are performed concurrently with the processing means executing instructions;
• and
• wherein the instruction type designating field is used to distinguish between arithmetic operations using data elements from the plurality of scalar registers or from the plurality of vector registers.

In a computer system having a main memory coupled to a processing unit by a plurality of vector registers, each vector register having a depth of a plurality of elements, a method of processing vector data comprising the steps of:

• (a) storing arrays of data elements as vector data in the main memory;
• (b) transferring a first set of unprocessed vector data from the main memory to the processing unit via a first vector register;
• (c) processing the first set of unprocessed vector data one data element at a time into a first set of processed vector data;
• (d) transferring the first set of processed vector data from the processing unit to a second vector register;
• (e) transferring a second set of unprocessed vector data from the main memory to a third vector register;
• (f) transferring the first set of processed vector data from the second vector register and the second set of unprocessed vector data from the third vector register to the processing unit;
• (g) processing the vector data from the second vector register and the third vector register one data element at a time into a second set of processed vector data;
• and
• (h) transferring the second set of processed vector data from the processing unit to a vector register other than the third vector register.

In a computer system having a main memory coupled to a processing unit by a plurality of vector registers, each vector register having a depth of a plurality of elements, a method of processing vector data comprising the steps of:

• (a) storing arrays of data elements as vector data in the main memory;
• (b) transferring a first set of unprocessed vector data from the main memory to the processing unit via a first vector register;
• (c) processing the first set of unprocessed vector data one data element at a time into a first set of processed vector data;
• (d) transferring the first set of processed vector data from the processing unit to a second vector register;
• (e) transferring the first set of processed vector data from the second vector register to the processing unit;
• (f) processing the vector data from the second vector register one data element at a time into a second set of processed vector data;
• and
• (g) transferring the second set of processed vector data from the processing unit to a vector register other than the second vector register.