Data processor and control circuit for inserting/extracting data to/from an optional byte position of a register

A data processor for executing instructions constituted by a digital instruction code including an operation specifying part, a source operand specifying part, information specifying a byte position in the source operand and a destination operand specifying part, comprising:

• instruction decoding means for decoding a digital instruction code, including a source operand specifying part of the instruction code, information specifying a byte position of said source operand, a destination operand specifying part of the instruction code and an operation specifying part of the instruction code and outputting a decoding result specifying a memory or source register corresponding to said source operand specifying part, a destination register corresponding to said destination operand specifying part, a position in the source data corresponding to said information specifying a byte position, and a length of the bit string to be inserted or extracted, comprising one or a plurality of bits, corresponding to said operation specifying part;
• a memory and a register file having one or a plurality of registers, at least one of the memory and the one or a plurality of registers being specified as the source operand by said decoding result;
• instruction executing means, connected to said instruction decoding means and receiving said decoding result, for writing and storing data in the destination specified by said decoding result and extracting a bit string, located at a position specified by said decoding result, from the data stored in said source operand specified by said decoding result;
• and
• instruction executing controlling means, connected to said instruction executing means, for operating said instruction executing means to write the bit string extracted by said instruction executing means into a position, which is specified by said decoding result, in the destination specified by said decoding result, when said operation specifying part decoded by said instruction decoding means is a specified code.

A control circuit for a data processor, comprising:

• a first register for storing and outputting source data;
• a second register for storing and outputting destination data;
• shifting means, connected to said first register, for obtaining data by shifting the source data outputted from said first register;
• and
• data writing means, connected to said second register and to said shifting means, for writing bits of the destination data outputted from said second register and bits of the data obtained by said shifting means, selectively in said second register;
• wherein operation is carried out by a plurality of steps for:
• reading a first data from said first register and inputting it to said shifting means;
• controlling said shifting means to shift said first data from the least significant bit toward the most significant bit by i bits, and to generate a second data;
• and
• controlling said data writing means to write a bit string of j bits from the "i+1"th bit from the least significant bit up to the "i+j"th bit of the second data into a bit string of j bits from the "i+1"th bit from the least significant bit up to the "i+j"th bit of said second register, and to write the original values of the respective bits again in other bits of said second register.

A control circuit for a data processor, comprising:

• a first register for storing and outputting source data;
• a second register for storing and outputting destination data;
• shifting means, connected to said first register, for shifting data outputted from said first register;
• and
• data writing means, connected to said second register and to said shifting means, for writing bits of the destination data outputted from said second register and bits of the data obtained by said shifting means, selectively in said second register;
• wherein operation is carried out by a plurality of steps for:
• reading a first data from said first register and inputting it to said shifting means;
• controlling said shifting means to shift said first data from the most significant bit toward the most significant bit by m bits, and to generate a second data;
• and
• controlling said data writing means to write a bit string of n bits from the least significant but up to the "n"th bit of the second data into a bit string of n bits from the least significant bit up to the "n"th bit of said second register, and to write the original values of the respective bits again in other bits of said second register.