US 5,669,009 AGranted

Signal processing array

AssigneeHughes Electronics Corporation

InventorsJerald A. Buktenica, Michael D. Yoo

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Abstract

A signal processing array architecture using a common multiport global memory to interface to a plurality of digital signal processors. The present architecture permits mixing of various types of digital signal processors, commercially available computers, and logic devices. The present signal processing architecture is comprised of a plurality of processing nodes (20) that each comprise a dual processor that is coupled to a local memory by way of a RAM loader bus. An emulated multiport memory is coupled to the dual processor by way of a local bus. A sensor bus is provided for transferring sensor signals from an external sensor to the emulated multiport memory. A global bus is provided that permits communication between each processing node. A bus controller is coupled between the emulated dual port memory and the sensor and global busses for controlling movement of signals to and from the emulated dual port memory. The present signal processing architecture provides a modular, programmable array of digital signal processors that has the flexibility to be used for different applications, thus reducing costs associated with any one application. Costs are also reduced by using commercially available processors. Modularity and programmability allow initial system development to proceed rapidly prior to the completion of processing algorithms and system specifications.

Claims3

Dependent claims

A modular signal processing array architecture comprising:

a plurality of processing nodes wherein each node comprises:
(a) a local memory comprising:
(i) first memory,
(ii) second memory, and
(ii) a dual port memory coupled between the first and second memories;
(b) a RAM loader bus coupled to the local memory;
(c) an emulated multiport memory comprising:
(i) a dual port memory coupled to data lines of the local bus, wherein semaphore and interrupt structure with modular bus arbitration is implemented in said dual port memory to permit inter-program communication between said processing nodes,
(ii) first global memory coupled to address lines of the local bus,
(iii) second global memory coupled to address lines of the local bus,
(iv) an input sensor memory coupled to the address lines of the local bus,
(v) a first FIFO buffer coupled to the first and second global memories and to the address lines of the local bus,
(vi) a register coupled between the first FIFO buffer and dual port memory and the global bus,
(vii) a second FIFO buffer coupled to the input sensor memory, to the address lines of the local bus, and to the local bus,
(viii) a second register coupled between the data lines of the local bus and the global memories, and
(ix) a third register coupled between the data lines of the local bus and the input sensor memory;
(d) a processor coupled to said RAM loader bus, comprising:
(i) first boot programmable read only memories for storing startup routines,
(ii) second boot programmable read only memory for storing startup routines,
(iii) first program memory for storing processing algorithms,
(iv) second program memory for strong processing algorithms,
(v) a memory loader controller coupled to the RAM loader bus and the first and second program memories for controlling the flow of data to and from the local memory,
(vi) first and second cache registers coupled to the local memory, and
(vii) first and second cache controllers coupled to the cache registers for controlling the flow of data to and from the local memory;
(e) a local bus coupled between the processor and the emulated multiport memory;
(f) a sensor bus for transferring sensor signals derived from an external sensor to the plurality of processing nodes;
(g) a global bus for coupling signals between the plurality of processing nodes, said global bus comprised of a time delay multiplexed bus;
and
(h) a bus controller coupled between the emulated multiport memory and the sensor and global busses for controlling movement of signals to and from the emulated multiport memory carried by the sensor and global busses.

26 more elements

A modular signal processing array architecture comprising:

a plurality of processing nodes wherein each node comprises:
(a) a local memory comprising:
(i) first memory,
(ii) second memory, and
(iii) a dual port memory coupled between the first and second memories;
(b) a RAM loader bus coupled to the local memory;
(c) an emulated multiport memory comprising:
(i) a dual port memory coupled to data lines of the local bus wherein semaphore and interrupt structure with modular bus arbitration is implemented in said dual port memory to permit inter-program communication between said processing nodes,
(ii) first global memory coupled to address lines of the local bus,
(iii) second global memory coupled to address lines of the local bus,
(iv) an input sensor memory coupled to the address line of the local bus,
(v) a first FIFO buffer coupled to the first and second global memories and to the address lines of the local bus,
(vi) a register coupled between the first FIFO buffer and dual port memory and the global bus,
(vii) a second FIFO buffer coupled to the input sensor memory, to the address lines of the local bus, and to the local bus,
(viii) a second register coupled between the data lines of the local bus and the global memories, and
(ix) a third register coupled between the data lines of the local bus and the input sensor memory;
(d) a dual processor comprising:
(i) data processors, and
(ii) signal processors;
(e) a local bus coupled between the dual processor and the emulated multiport memory;
(f) a sensor bus for transferring sensor signals derived from an external sensor to the plurality of processing nodes;
(g) a global bus for coupling signs between the plurality of processing nodes, said global bus comprised of a time delay multiplexed bus;
and
(g) a bus controller coupled between the emulated multiport memory and the sensor and global busses for controlling movement of signals to and from the emulated multiport memory carried by the sensor and global busses.

21 more elements

A modular signal processing array architecture comprising:

a plurality of processing nodes wherein each node comprises:
(a) a local memory comprising:
(i) first memory,
(ii) second memory, and
(iii) a dual port memory coupled between the first and second memories;
(b) a RAM loader bus coupled to the local memory;
(c) an emulated multiport memory comprising:
(i) a dual port memory coupled to data lines of the local bus, wherein semaphore and interrupt structure with modular bus arbitration is implemented in said dual port memory to permit inter-program communication between said processing nodes,
(ii) first global memory coupled to address lines of the local bus,
(iii) second global memory coupled to address lines of the local bus,
(iv) an input sensor memory coupled to the address lines of the local bus,
(v) a first FIFO buffer coupled to the first and second global memories and to the address lines of the local bus,
(vi) a register coupled between the first FIFO buffer and dual port memory and the global bus,
(vii) a second FIFO buffer coupled to the input sensor memory, to the address lines of the local bus, and to the local bus,
(viii) a second register coupled between the data lines of the local bus and the global memories, and
(ix) a third register coupled between the data lines of the local bus and the input sensor memory;
(d) a logic device;
(e) a local bus coupled between the logic device and the emulated multiport memory;
(f) a sensor bus for transferring sensor signals derived from an external sensor to the plurality of processing nodes;
(g) a global bus for coupling signals between the plurality of processing nodes, said global bus comprised of a time delay multiplexed bus;
(h) a bus controller coupled between the emulated multiport memory and the sensor and global busses for controlling movement of signals to and from the emulated multiport memory carried by the sensor and global busses;
and
(i) a memory address generator coupled to the logic device for reading and writing data from and to the local memory and the emulated multiport memory.

20 more elements

Dependencies are inferred from the claim text.