Method of monitoring system bus traffic by a CPU operating with reduced power

In a data processing system including first and second microprocessors each having internal logic that includes a data cache and a bus unit coupled to a system bus, a method of system operation to maintain cache coherency comprising the steps of:

• (a) reducing the power consumption of the first microprocessor by decoupling a clock signal to a majority of the internal logic of the first microprocessor, but still coupling the clock signal to the bus interface of the first microprocessor;
• (b) starting a write cycle on the system bus by the second microprocessor to request a cache line of data;
• (c) snooping the write cycle on the system bus by the bus interface of the first microprocessor while reducing the power consumption of the first microprocessor;
• and
• (d) signaling to the second microprocessor by the first microprocessor that a modified cache line of the data is stored in the data cache of the first microprocessor while reducing the power consumption of the first microprocessor.