Object code compatible representation of very long instruction word programs

Abstract

Object code compatibility is provided among VLIW processors with different organizations. The object code can be executed by sequential processors, thus providing backward compatibility with scalar and superscalar processors. A mechanism is provided which allows representing VLIW programs in an implementation independent manner. This mechanism relies on instruction cache (I-cache) reload/access processes which incorporate implementation-dependent features into a VLIW program. In this way, programs are represented in main memory in an implementation independent manner (i.e., without reflecting the organization of the processor where they are executed), the implementation-specific aspects are introduced as part of the instruction cache reload/fetch processes, and the simplicity in instruction dispatch logic that is characteristic of VLIW processors is preserved. This allows for object code compatibility among VLIW processors with different organizations. This is done by decomposing the process into tasks performed at I-cache reload time and tasks performed at I-cache access time, requiring simpler logic to perform the translation. The resulting VLIWs can be executed starting from any operation within them (e.g., branching into them is possible), and there is a one-to-one correspondence among primitive operations in main memory and in the I-cache. Moreover, a framework is provided for generating (compiling) code which exploits the parallel execution features of a VLIW processor (parallelized code) which is also executable by a sequential processor without unduly affecting performance.

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