Decoder having a split queue system for processing intstructions in a first queue separate from their associated data processed in a second queue

In a split queue system for a decoder having a main queue coupled to the decoder, a next processing stage coupled to the main queue, a shadow queue coupled to the decoder, a control circuit coupled to the main queue and the shadow queue, a branch address calculator coupled to the shadow queue, a constant ROM coupled to the output of the shadow queue and a selector, a method of decoding instructions comprising:

• (a) receiving instruction in the decoder;
• (b) transmitting a micro-operation from the instruction to the main queue;
• (c) transmitting data associated with the micro-operation to the shadow queue;
• (d) outputting a processed micro-operation from the main queue in a first clock cycle;
• and
• (e) outputting data associated with the micro-operation from the shadow queue in a second clock cycle.

A pipelined processor comprising:

• a main memory for storing instructions and data;
• a cache memory for storing frequently accessed data;
• a system bus coupled to the main memory and the cache memory;
• a main memory control coupled to the system bus;
• an instruction fetch unit coupled to the system bus for fetching instructions and;
• a decoder unit for decoding instructions fetched by the instruction fetch unit, the decoder unit including:
• a split queue system for a decoder, the split queue system being configured to decode an instruction's micro-operations separate from each micro-operation's associated data, said split queue system comprising:
• a main queue coupled to receive a micro-operation from a decoder;
• a next processing stage coupled to receive the micro-operation issued from the main queue and to process the micro-operation in one cycle to provide a processed micro-operation;
• a shadow queue coupled to receive the micro-operation's associated data from the decoder;
• and
• a control circuit coupled to the main queue and the shadow queue for issuing the micro-operation from the main queue in a first cycle and issuing data associated with the micro-operation in a second cycle so that the data is synchronized with its associated processed micro-operation.