US 5,668,984 A · Variable stage load path and method of operation

Abstract

A floating point processing system and method of operation are disclosed. Single word precision denormalized operands and also misaligned operands are detected while such operands are being loaded into the first stage of a pipelined floating point unit. Such operands are aligned to a double word boundary and/or single word operands are normalized by a processing stages inserted into the pipe ahead of the first stage of the pipelined floating point unit thereby entering a one stage delay. In this way, misaligned operands and single word denormalized operands can be processed without the need for example to cancel the instruction, execute a normalize or alignment instruction and then re-launch the original instruction.

Claims22

Dependent claims

A digital number processing system, comprising:

a multiple stage pipelined unit for executing instructions to perform operations on operands;
and
a variable stage load path connected to a source of operands and connected to said pipelined unit for providing said operands to said pipelined unit, said variable stage load path further comprising:
control means for detecting whether an operand is in a valid form while said operand is being loaded into a first stage of said pipelined unit, said control means staging execution of an instruction when said operand is in invalid form;
logic means for converting said operand to a valid form while said operand would otherwise be processed by said first stage of said pipelined unit thereby introducing one stage of delay;
gate means for presenting said converted operand to said pipelined unit for processing after said one stage of delay.

3 more elements

Dependencies are inferred from the claim text.

Variable stage load path and method of operation

Life of this patent

Variable stage load path and method of operation

Life of this patent

Abstract

Claims22