Precise stopping of a high speed microprocessor clock
AssigneeInternational Business Machines Corporation
InventorsRobert Maurice Houle, Kenneth Michael Zick
Life of this patent
Estimating the term…
Abstract
A method and means for selectively stopping the internal clock of a microprocessor on any of 16 phases using functional components which include: a clock multiplier circuit, that receives a clock signal input from an external oscillator or other appropriate source, and outputs the internal clock signal for the microprocessor; control logic circuitry for processing and inputting stop signals to the clock multiplier; and a clock special purpose register, which provides control signals to the control logic circuitry to determine when stopping of the internal clock signal should occur.
Claims18
Apparatus for precisely controlling the stopping of a microprocessor internal multiphase clock, comprising:
- means for receiving an external clock signal and deriving an internal clock signal therefrom with a frequency that is a multiple of the frequency of said external clock signal and with each cycle of said external clock signal being divided into a plurality of phases;
- and
- means for selectively stopping said internal clock on each of said phases.
A method for precisely controlling the stopping of a microprocessor internal multiphase clock, comprising the steps of:
- receiving an external clock signal and deriving an internal clock signal from said external clock signal, said internal clock signal's frequency being a multiple of the frequency of said external clock signal and each cycle of said external clock signal being divided into a plurality of phases;
- and selectively stopping said internal clock on each of said phases.
Dependencies are inferred from the claim text.