System and method for using a half-clock module to implement computer timing control circuitry
AssigneeNational Semiconductor Corporation
InventorIan E. Davis
Life of this patent
Estimating the term…
Abstract
A computer timing control apparatus including, and a method of using, a controller for providing a toggle-rising signal and a toggle-falling signal, and a half-clock module for sampling the toggle-rising signal and the toggle-falling signal, and generating a module output signal which toggles on the rising edge of the system clock signal if the toggle-rising signal is asserted when sampled, and toggles on the next falling edge of the system clock signal if the toggle-falling signal is asserted when sampled.
Claims20
A half-clock timing control module comprising:
- clock signal input means for receiving a system clock signal;
- control signal input means for receiving module control signals;
- module means responsive to the clock signal and the module control signals for generating a module output signal which changes state on selected rising and falling edges of the system clock signal;
- and
- module signal output means for providing the module output signal.
A timing control device comprising:
- a system clock signal input for receiving a system clock signal having alternating rising edges and falling edges;
- toggle-control signal inputs for receiving toggle-control signals including a toggle-rising signal and a toggle-falling signal which have an asserted state and a deasserted state;
- and
- a half-clock module for generating a module output signal by, on each rising edge of the system clock signal, sampling the toggle-rising signal and the toggle-falling signal, and when the sampled toggle-rising signal is asserted, toggling the module output signal, and when the sampled toggle-falling signal is asserted, toggling the module output signal on the next falling edge of the system clock signal.
A method of generating a digital timing control signal comprising the steps of:
- receiving a system clock signal having alternating rising edges and falling edges;
- receiving toggle-control signals including a toggle-rising signal and a toggle-falling signal;
- sampling the toggle-control signals on the rising edges of the system clock signal;
- and
- generating a half-clock module output signal by, on each rising edge of the system clock signal, sampling the toggle-rising signal and the toggle-falling signal, and when the sampled toggle-rising signal is asserted, toggling the module output signal, and when the sampled toggle-falling signal is asserted, toggling the module output signal on the next falling edge of the system clock signal.
Half-clock design module means comprising:
- means for receiving a system clock signal having alternating rising edges and falling edges;
- means for receiving toggle-control signals including a toggle-rising signal and a toggle-falling signal;
- means for sampling the toggle-control signals on the rising edges of the system clock signal;
- and
- means for generating a half-clock module output signal by, on each rising edge of the system clock signal, sampling the toggle-rising signal and the toggle-falling signal, and when the sampled toggle-rising signal is asserted, toggling the module output signal, and when the sampled toggle-falling signal is asserted, toggling the module output signal on the next falling edge of the system clock signal.
Dependencies are inferred from the claim text.