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US 5,668,976 AGranted
Error correction method and apparatus for disk drive emulator
AssigneeCirrus Logic, Inc.
InventorChristopher P. Zook
Life of this patent
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AssigneeCirrus Logic, Inc.
InventorChristopher P. Zook
Estimating the term…
An error correction system (10) is provided for correcting up to two bits per sector stored in a solid state non-volatile memory (12) which emulates a disk drive. The error correction system (10) includes an ECC/remainder generator (100), a bank of remainder registers (102), and a calculation circuit (104), all under supervision of a controller (106). During a write-to-memory operation, error correction system (10) generates ECC bytes for storage in the memory (12). In a write operation, an entire sector acquired from memory (12) is used to generate ECC check remainder bytes REM.sub.0 -REM.sub.3. The check remainder bytes REM.sub.0 -REM.sub.3 are utilized to generates syndromes S.sub.1, S.sub.3 and a factor S.sub.B, the syndromes in turn being used to obtain either one or two error location positions (.alpha..sup.L1, .alpha..sup.L2). The mathematical calculation circuit (104) not only generates the syndromes S.sub.1, S.sub.3 and factor S.sub.B, as well as the error location positions (.alpha..sup.L1, .alpha..sup.L2), but also generates the addresses of the bit errors in the sector (L1-64 [complemented], L2-64[complemented].
An error correction system for a solid state disk drive which emulates the operation of a magnetic disk drive, the error correction system comprising:
An error correction method for a solid state disk drive which emulates the operation of a magnetic disk drive, the error correction method comprising:
An error correction system for a solid state disk drive which emulates the operation of a magnetic disk drive, the error correction system correcting as many as two errors per sector applied to the system by the solid state disk drive by using a 32 bit code generator polynomial, the 32 bit code generator polynomial being the product of two 14-bit polynomials and a 4-bit polynomial, and wherein the 4-bit polynomial is used to generate a range check factor for determining whether error(s) occurred in a data portion of the sector.
An error correction system for a solid state disk drive, the error correction system using a generator polynomial which is the product of three polynomials, the error correction system comprising:
An error correction system for correcting a sector of data received from a solid state disk drive, the error correction system employing a code generator polynomial which has a code generator length greater than necessary for correcting as many as two errors per sector applied to the error correction system by the solid state disk drive, the code generator polynomial being utilized by the system to generate at least one syndrome and a range check factor.
Dependencies are inferred from the claim text.