Memory with variable levels of interleaving and associated configurator circuit

A configurator circuit for a memory having variable levels of interleaving, said memory comprising a plurality of independently addressable modules each having a capacity equal to either a basic capacity or a multiple of said basic capacity, wherein said memory is addressed by memory addresses each comprising at least a first field of lower order bits and a second field of higher order bits, and wherein said modules are each selectable by one of a plurality of module selection signals in accordance with an interleaving level dependent of the number and capacities of said modules, and said modules are addressed by module addresses comprising portions of said memory addresses, said configurator circuit comprising:

• a memory device addressed by said second field to output an interleaving signal and an interleaving code, said interleaving code representing an interleaving level associated with said second field if said first signal is at first level and representing a module selection code if said first signal is at a second level;
• a plurality of registers each storing a module selection code associated with one of a plurality of interleaving levels;
• and
• selection and decoding means, coupled to said plurality of registers and said memory device, for selecting one among said interleaving code and said module selection codes stored in said plurality of registers and for decoding said one selected code into one of said plurality of module selection signals, said selection and decoding means being controlled by at least a portion of said first field, said interleaving signal, and said interleaving code.

A variable interleaving level memory comprising:

• a plurality of independently addressable memory modules at least two of which have different storage capacities;
• and
• a configurator circuit receiving portions of successive memory addresses addressing said memory and successively outputting module selection codes and bit selection codes for successive memory addresses, said module selection codes addressing at least some of said memory modules or parts thereof at a first interleaving level for first values of said memory address portions and addressing at least some of said memory modules or parts thereof at a second or no interleaving level for second values of said memory address portions;
• and
• a selection circuit coupled to said configurator circuit and receiving high and low order bits of said memory addresses for selecting based on said bit selection codes which of said high or low order bits to pass as module address bits for addressing locations within said modules.