Address selective emulation routine pointer address mapping system

An address selective address mapping system for a host computer system having a central processing unit (CPU) having data inputs and instruction address outputs, and a memory having instruction address inputs and data outputs, the data inputs of said CPU and the data outputs of said memory coupled to a data bus and an instruction bus, the address selective address mapping system for selectively mapping a memory address output by said CPU to a cache address, the memory address and the cache address each containing a pointer to an emulation routine, the address selective address mapping system comprising:

• an instruction mapping circuit having inputs and outputs for receiving and selectively translating the memory address into a corresponding cache address, the inputs of the instruction mapping circuit coupled to instruction address outputs of the CPU and the outputs of the instruction mapping circuit coupled to instruction address inputs of the memory;]
• an instruction cache having control inputs, address inputs and data inputs and data outputs for storing a plurality of pointers, each pointer corresponding to an emulation routine, the data inputs and data outputs of said instruction cache coupled to an instruction bus, and the address inputs of the instruction cache coupled to an instruction bus;
• a data cache having address inputs, data inputs and data outputs for storing data, the data inputs and data outputs of said data cache coupled to said data bus, and the address inputs of said data cache coupled to a data address bus;
• a decoder having inputs and an output for controlling whether an address received from said CPU is subject to being translated to an instruction cache address by determining whether the address received corresponds to an address at which a pointer to an emulation routine for a source instruction is stored, the inputs of said decoder coupled to receive an address signal from said CPU;
• an address translation circuit having inputs and outputs for determining whether the address received corresponds to a source instruction that has a corresponding pointer to an emulation routine stored in said instruction cache, the inputs of said address translation circuit coupled to receive an entire address signal from said CPU;
• and
• an address selection means having a control input, first data inputs, second data inputs and outputs, said address selection means receiving signals at the first data inputs and the second data inputs and selectively outputting the signals from the first data inputs and the second data inputs, the control input of said address selection means coupled to the output of said decoder, the first data inputs coupled to the outputs of said address translation circuit, the second data inputs coupled to receive an entire address signal from said CPU, and the outputs of said address selection means coupled to the address inputs of said instruction cache and the address inputs of said memory.

An address selective address mapping circuit for receiving and selectively translating a memory address into a corresponding cache address, the address selective address mapping circuit comprising:

• a decoder having inputs and an output for controlling whether an address received from a CPU is subject to being translated to a cache address by determining whether the address received corresponds to an address at which a pointer to an emulation routine for a source instruction within a source instruction set is stored, the inputs of said decoder coupled to receive an address signal from said CPU;
• an address translation circuit having inputs and outputs for determining whether the address received corresponds to a source instruction that has a corresponding pointer to an emulation routine stored in a cache, the inputs of said address translation circuit coupled to receive an entire address signal from said CPU;
• and
• an address selection means having a control input, first data inputs, second data inputs and outputs, said address selection means receiving signals at the first data inputs and the second data inputs and selectively outputting the signals from the first data inputs and the second data inputs, the control input of said address selection means coupled to the output of said decoder, the first data inputs coupled to the outputs of said address translation circuit, the second data inputs coupled to receive an entire address signal from said CPU, and the outputs of said address selection means coupled to the address inputs of said cache and the address inputs of a memory.