US 5,668,967 A · Apparatus and methods for reducing numbers of read-modify-write cycles to a memory, and for improving DMA efficiency

Abstract

Disclosed are methods and apparatus for interfacing a central processor (12) (CP) and an IO controller (30) (IOC) to a main memory (40). A CP and an IO write buffer each include a pair of memory input data registers, located in a pair of Memory Data Unit (MDU) integrated circuits (38a, 38b), and also two memory address registers, a previous memory address register, and an address comparator, located in a Memory Address Unit (MAU) (36). These registers, in conjunction with associated control logic, are used to buffer CP and IO write addresses and data to the main memory. If both address registers have a pending write, the last loaded address register is checked for a match against the current write address using the previous address register and the comparator. A match results in the combination of the previous write data and the current write data into one pending write, using write merge circuitry within the MDUs. IO read operations are performed by first loading the MDU read data registers with read data from memory locations specified by a quad-word aligned address in the first IO address register, followed by an incremented quad-word aligned address in the second IO address register. The transfer is then begun and all incoming IO read addresses are checked for a current quad-word compare. If an incoming quad-word aligned IO read address is not equal to the content of the IO previous address register, a memory read request is generated using the incremented address, and the MDU read data registers are advanced. A feature of this invention is that no specific addresses are used, and a knowledge of a transfer width (byte, word, etc.) is not required to determine memory operation types.

Claims14

Dependent claims

A data processing system having a central processor (CP), a memory, an address bus coupled to said CP having signal lines for conveying memory addresses that are generated by said CP, and a data bus coupled to said CP for transferring data to and from said CP for memory read and memory write operations, respectively, said system further comprising:

address buffer means connected within said address bus between said CP and said memory for receiving and buffering memory addresses that are generated by said CP, said address buffer means comprising,
a plurality of distinct address registers, each of said plurality of distinct address registers having a width sufficient for storing a first portion of a memory address received from said CP during a CP write to memory operation, said plurality of distinct address registers including a first address register for storing a first portion of a first memory address received from said CP during a CP write to memory operation, and a second address register for storing a duplicate copy of said first portion of said first memory address received from said CP during a CP write to memory operation, said stored first portion of said first memory address being a content of said second address register;
and
comparator means having a first input that is coupled to an output of said second address register and a second input that is coupled to said address bus, for comparing said first portion of a second memory address that is received from said CP to said content of said second address register, said comparator means having an output for indicating, when in a first state, that (a) said first portion of said second memory address that is received from said CP is equal to said content of said second address register, and that (b) a write to memory operation for which said second memory address is generated can be combined with an as yet unexecuted write to memory operation for which said first memory address was generated.

1 more element

A data processing system having an Input/Output controller (IOC), a memory, an address bus coupled to said IOC having signal lines for conveying memory addresses that are generated by said IOC, and a data bus coupled to said IOC for transferring data to and from said IOC during memory read and write operations, respectively, said system further comprising:

address buffer means connected within said address bus between said IOC and said memory for buffering a plurality of memory addresses that are generated by said IOC, said address buffer means comprising,
a plurality of distinct address registers, each of said plurality of distinct address registers having a width sufficient for storing a first portion of a memory address received from said IOC during an IOC write to memory operation, said plurality of distinct address registers including a first address register for storing a first portion of a first memory address received from said IOC during an IOC write to memory operation, and a second address register for storing a duplicate copy of said first portion of said first memory address received from said IOC during an IOC write to memory operation, said stored first portion of said first memory address being a content of said second address register;
and
comparator means having a first input that is coupled to an output of said second address register and a second input that is coupled to said address bus, for comparing said first portion of a second memory address that is received from said IOC to said content of said second address register, said comparator means having an output for indicating, when in a first state, that (a) said first portion of said second memory address that is received from said IOC is equal to said content of said second address register, and that (b) a write to memory operation for which said second memory address is generated can be combined with an as yet unexecuted write to memory operation for which said first memory address was generated.

1 more element

A data processing system having a central processor (CP), an Input/Output Controller (IOC), a memory, a first address bus coupled to said CP having signal lines for conveying memory addresses that are generated by said CP, a second address bus coupled to said IOC having signal lines for conveying memory addresses that are generated by said IOC, a first data bus coupled to said CP for transferring data to and from said CP for memory read and memory write operations, respectively, and a second data bus coupled to said IOC for transferring data to and from said IOC for memory read and memory write operations, respectively, said system further comprising:

first address buffer means connected within said first address bus between said CP and said memory for receiving and buffering memory addresses that are generated by said CP, said first address buffer means comprising,
a first plurality of distinct address registers, each of said first plurality of distinct address registers having a width sufficient for storing a first portion of a memory address received from said CP during a CP write to memory operation, said first plurality of distinct address registers including a first CP address register for storing a first portion of a first memory address received from said CP during a CP write to memory operation, and a second CP address register for storing a duplicate copy of said first portion of said first memory address received from said CP during a CP write to memory operation, said stored first portion of said first memory address being a content of said second CP address register;
first comparator means having a first input that is coupled to an output of said second CP address register and a second input that is coupled to said first address bus, for comparing said first portion of a second memory address that is received from said CP to said content of said second CP address register, said comparator means having an output for indicating, when in a first state, that (a) said first portion of said second memory address that is received from said CP is equal to said content of said second CP address register, and that (b) a write to memory operation for which said second memory address is generated by said CP can be combined with an as yet unexecuted write to memory operation for which said first memory address was generated by said CP;
second address buffer means connected within said second address bus between said IOC and said memory for buffering a plurality of memory addresses that are generated by said IOC, said second address buffer means comprising,
a second plurality of distinct address registers, each of said second plurality of distinct address registers having a width sufficient for storing a first portion of a memory address received from said IOC during an IOC write to memory operation, said second plurality of distinct address registers including a first IOC address register for storing a first portion of a first memory address received from said IOC during an IOC write to memory operation, and a second IOC address register for storing a duplicate copy of said first portion of said first memory address received from said IOC during an IOC write to memory operation, said stored first portion of said first memory address being a content of said second IOC address register;
and
second comparator means having a first input that is coupled to an output of said second IOC address register and a second input that is coupled to said second address bus, for comparing said first portion of a second memory address that is received from said IOC to said content of said second IOC address register, said comparator means having an output for indicating, when in a first state, that (a) said first portion of said second memory address that is received from said IOC is equal to said content of said second IOC address register, and that (b) a write to memory operation for which said second memory address is generated by said IOC can be combined with an as yet unexecuted write to memory operation for which said first memory address was generated by said IOC.

4 more elements

Dependencies are inferred from the claim text.

Apparatus and methods for reducing numbers of read-modify-write cycles to a memory, and for improving DMA efficiency

Life of this patent

Apparatus and methods for reducing numbers of read-modify-write cycles to a memory, and for improving DMA efficiency

Life of this patent

Abstract

Claims14